#include "hail-os-dep.h" /* macros for mask and shift */ #define RX_RX_MASK 0xFF #define RX_RX_SHIFT 0x0 #define RX_RX_VAL(x) (((x) << RX_RX_SHIFT) & RX_RX_MASK) #define RX_RSV_8_31_MASK 0xFFFFFF00 #define RX_RSV_8_31_SHIFT 0x8 #define RX_RSV_8_31_VAL(x) (((x) << RX_RSV_8_31_SHIFT) & RX_RSV_8_31_MASK) #define TX_TX_MASK 0xFF #define TX_TX_SHIFT 0x0 #define TX_TX_VAL(x) (((x) << TX_TX_SHIFT) & TX_TX_MASK) #define TX_RSV_8_31_MASK 0xFFFFFF00 #define TX_RSV_8_31_SHIFT 0x8 #define TX_RSV_8_31_VAL(x) (((x) << TX_RSV_8_31_SHIFT) & TX_RSV_8_31_MASK) #define DLL_DLL_MASK 0xFF #define DLL_DLL_SHIFT 0x0 #define DLL_DLL_VAL(x) (((x) << DLL_DLL_SHIFT) & DLL_DLL_MASK) #define DLL_RSV_8_31_MASK 0xFFFFFF00 #define DLL_RSV_8_31_SHIFT 0x8 #define DLL_RSV_8_31_VAL(x) (((x) << DLL_RSV_8_31_SHIFT) & DLL_RSV_8_31_MASK) #define DLM_DLM_MASK 0xFF #define DLM_DLM_SHIFT 0x0 #define DLM_DLM_VAL(x) (((x) << DLM_DLM_SHIFT) & DLM_DLM_MASK) #define DLM_RSV_8_31_MASK 0xFFFFFF00 #define DLM_RSV_8_31_SHIFT 0x8 #define DLM_RSV_8_31_VAL(x) (((x) << DLM_RSV_8_31_SHIFT) & DLM_RSV_8_31_MASK) #define IER_DMAE_MASK 0x80 #define IER_DMAE_SHIFT 0x7 #define IER_DMAE_VAL(x) (((x) << IER_DMAE_SHIFT) & IER_DMAE_MASK) #define IER_UUE_MASK 0x40 #define IER_UUE_SHIFT 0x6 #define IER_UUE_VAL(x) (((x) << IER_UUE_SHIFT) & IER_UUE_MASK) #define IER_NRZE_MASK 0x20 #define IER_NRZE_SHIFT 0x5 #define IER_NRZE_VAL(x) (((x) << IER_NRZE_SHIFT) & IER_NRZE_MASK) #define IER_RTOIE_MASK 0x10 #define IER_RTOIE_SHIFT 0x4 #define IER_RTOIE_VAL(x) (((x) << IER_RTOIE_SHIFT) & IER_RTOIE_MASK) #define IER_MSI_MASK 0x8 #define IER_MSI_SHIFT 0x3 #define IER_MSI_VAL(x) (((x) << IER_MSI_SHIFT) & IER_MSI_MASK) #define IER_RLSI_MASK 0x4 #define IER_RLSI_SHIFT 0x2 #define IER_RLSI_VAL(x) (((x) << IER_RLSI_SHIFT) & IER_RLSI_MASK) #define IER_THRI_MASK 0x2 #define IER_THRI_SHIFT 0x1 #define IER_THRI_VAL(x) (((x) << IER_THRI_SHIFT) & IER_THRI_MASK) #define IER_RDI_MASK 0x1 #define IER_RDI_SHIFT 0x0 #define IER_RDI_VAL(x) (((x) << IER_RDI_SHIFT) & IER_RDI_MASK) #define IER_RSV_8_31_MASK 0xFFFFFF00 #define IER_RSV_8_31_SHIFT 0x8 #define IER_RSV_8_31_VAL(x) (((x) << IER_RSV_8_31_SHIFT) & IER_RSV_8_31_MASK) #define IIR_FIFOES_MASK 0xC0 #define IIR_FIFOES_SHIFT 0x6 #define IIR_FIFOES_VAL(x) (((x) << IIR_FIFOES_SHIFT) & IIR_FIFOES_MASK) /* value options for bit IIR_FIFOES */ #define IIR_NON_FIFIO 0 #define IIR_FIFO 3 #define IIR_EOC_MASK 0x20 #define IIR_EOC_SHIFT 0x5 #define IIR_EOC_VAL(x) (((x) << IIR_EOC_SHIFT) & IIR_EOC_MASK) #define IIR_ABL_MASK 0x10 #define IIR_ABL_SHIFT 0x4 #define IIR_ABL_VAL(x) (((x) << IIR_ABL_SHIFT) & IIR_ABL_MASK) #define IIR_TOD_MASK 0x8 #define IIR_TOD_SHIFT 0x3 #define IIR_TOD_VAL(x) (((x) << IIR_TOD_SHIFT) & IIR_TOD_MASK) #define IIR_ID_MASK 0x6 #define IIR_ID_SHIFT 0x1 #define IIR_ID_VAL(x) (((x) << IIR_ID_SHIFT) & IIR_ID_MASK) /* value options for bit IIR_ID */ #define IIR_MSI 0 #define IIR_THRI 1 #define IIR_RDI 2 #define IIR_RLSI 3 #define IIR_NO_INT_MASK 0x1 #define IIR_NO_INT_SHIFT 0x0 #define IIR_NO_INT_VAL(x) (((x) << IIR_NO_INT_SHIFT) & IIR_NO_INT_MASK) #define IIR_RSV_8_31_MASK 0xFFFFFF00 #define IIR_RSV_8_31_SHIFT 0x8 #define IIR_RSV_8_31_VAL(x) (((x) << IIR_RSV_8_31_SHIFT) & IIR_RSV_8_31_MASK) #define FCR_TRIGGER_MASK_MASK 0xC0 #define FCR_TRIGGER_MASK_SHIFT 0x6 #define FCR_TRIGGER_MASK_VAL(x) (((x) << FCR_TRIGGER_MASK_SHIFT) & FCR_TRIGGER_MASK_MASK) /* value options for bit FCR_TRIGGER_MASK */ #define FCR_TRIGGER_1 0 #define FCR_TRIGGER_8 1 #define FCR_TRIGGER_16 2 #define FCR_TRIGGER_14 3 #define FCR_BUS_MASK 0x20 #define FCR_BUS_SHIFT 0x5 #define FCR_BUS_VAL(x) (((x) << FCR_BUS_SHIFT) & FCR_BUS_MASK) #define FCR_TRAIL_MASK 0x10 #define FCR_TRAIL_SHIFT 0x4 #define FCR_TRAIL_VAL(x) (((x) << FCR_TRAIL_SHIFT) & FCR_TRAIL_MASK) #define FCR_DMA_SELECT_MASK 0x8 #define FCR_DMA_SELECT_SHIFT 0x3 #define FCR_DMA_SELECT_VAL(x) (((x) << FCR_DMA_SELECT_SHIFT) & FCR_DMA_SELECT_MASK) #define FCR_CLEAR_XMIT_MASK 0x4 #define FCR_CLEAR_XMIT_SHIFT 0x2 #define FCR_CLEAR_XMIT_VAL(x) (((x) << FCR_CLEAR_XMIT_SHIFT) & FCR_CLEAR_XMIT_MASK) #define FCR_CLEAR_RCVR_MASK 0x2 #define FCR_CLEAR_RCVR_SHIFT 0x1 #define FCR_CLEAR_RCVR_VAL(x) (((x) << FCR_CLEAR_RCVR_SHIFT) & FCR_CLEAR_RCVR_MASK) #define FCR_ENABLE_FIFO_MASK 0x1 #define FCR_ENABLE_FIFO_SHIFT 0x0 #define FCR_ENABLE_FIFO_VAL(x) (((x) << FCR_ENABLE_FIFO_SHIFT) & FCR_ENABLE_FIFO_MASK) #define FCR_RSV_8_31_MASK 0xFFFFFF00 #define FCR_RSV_8_31_SHIFT 0x8 #define FCR_RSV_8_31_VAL(x) (((x) << FCR_RSV_8_31_SHIFT) & FCR_RSV_8_31_MASK) #define LCR_DLAB_MASK 0x80 #define LCR_DLAB_SHIFT 0x7 #define LCR_DLAB_VAL(x) (((x) << LCR_DLAB_SHIFT) & LCR_DLAB_MASK) #define LCR_SBC_MASK 0x40 #define LCR_SBC_SHIFT 0x6 #define LCR_SBC_VAL(x) (((x) << LCR_SBC_SHIFT) & LCR_SBC_MASK) #define LCR_SPAR_MASK 0x20 #define LCR_SPAR_SHIFT 0x5 #define LCR_SPAR_VAL(x) (((x) << LCR_SPAR_SHIFT) & LCR_SPAR_MASK) #define LCR_EPAR_MASK 0x10 #define LCR_EPAR_SHIFT 0x4 #define LCR_EPAR_VAL(x) (((x) << LCR_EPAR_SHIFT) & LCR_EPAR_MASK) /* value options for bit LCR_EPAR */ #define LCR_ODD_PARITY 0 #define LCR_EVEN_PARITY 1 #define LCR_PARITY_MASK 0x8 #define LCR_PARITY_SHIFT 0x3 #define LCR_PARITY_VAL(x) (((x) << LCR_PARITY_SHIFT) & LCR_PARITY_MASK) /* value options for bit LCR_PARITY */ #define LCR_PARITY 0 #define LCR_NO_PARITY 1 #define LCR_STOP_MASK 0x4 #define LCR_STOP_SHIFT 0x2 #define LCR_STOP_VAL(x) (((x) << LCR_STOP_SHIFT) & LCR_STOP_MASK) /* value options for bit LCR_STOP */ #define LCR_STOP_BIT_1 0 #define LCR_STOP_BIT_2 1 #define LCR_WLS_MASK 0x3 #define LCR_WLS_SHIFT 0x0 #define LCR_WLS_VAL(x) (((x) << LCR_WLS_SHIFT) & LCR_WLS_MASK) /* value options for bit LCR_WLS */ #define LCR_WLEN5 0 #define LCR_WLEN6 1 #define LCR_WLEN7 2 #define LCR_WLEN8 3 #define LCR_RSV_8_31_MASK 0xFFFFFF00 #define LCR_RSV_8_31_SHIFT 0x8 #define LCR_RSV_8_31_VAL(x) (((x) << LCR_RSV_8_31_SHIFT) & LCR_RSV_8_31_MASK) #define LSR_FIFOE_MASK 0x80 #define LSR_FIFOE_SHIFT 0x7 #define LSR_FIFOE_VAL(x) (((x) << LSR_FIFOE_SHIFT) & LSR_FIFOE_MASK) #define LSR_TEMT_MASK 0x40 #define LSR_TEMT_SHIFT 0x6 #define LSR_TEMT_VAL(x) (((x) << LSR_TEMT_SHIFT) & LSR_TEMT_MASK) #define LSR_THRE_MASK 0x20 #define LSR_THRE_SHIFT 0x5 #define LSR_THRE_VAL(x) (((x) << LSR_THRE_SHIFT) & LSR_THRE_MASK) #define LSR_BI_MASK 0x10 #define LSR_BI_SHIFT 0x4 #define LSR_BI_VAL(x) (((x) << LSR_BI_SHIFT) & LSR_BI_MASK) #define LSR_FE_MASK 0x8 #define LSR_FE_SHIFT 0x3 #define LSR_FE_VAL(x) (((x) << LSR_FE_SHIFT) & LSR_FE_MASK) #define LSR_PE_MASK 0x4 #define LSR_PE_SHIFT 0x2 #define LSR_PE_VAL(x) (((x) << LSR_PE_SHIFT) & LSR_PE_MASK) #define LSR_OE_MASK 0x2 #define LSR_OE_SHIFT 0x1 #define LSR_OE_VAL(x) (((x) << LSR_OE_SHIFT) & LSR_OE_MASK) #define LSR_DR_MASK 0x1 #define LSR_DR_SHIFT 0x0 #define LSR_DR_VAL(x) (((x) << LSR_DR_SHIFT) & LSR_DR_MASK) #define LSR_RSV_8_31_MASK 0xFFFFFF00 #define LSR_RSV_8_31_SHIFT 0x8 #define LSR_RSV_8_31_VAL(x) (((x) << LSR_RSV_8_31_SHIFT) & LSR_RSV_8_31_MASK) #define MCR_RSV_6_31_MASK 0xFFFFFFC0 #define MCR_RSV_6_31_SHIFT 0x6 #define MCR_RSV_6_31_VAL(x) (((x) << MCR_RSV_6_31_SHIFT) & MCR_RSV_6_31_MASK) #define MCR_AFE_MASK 0x20 #define MCR_AFE_SHIFT 0x5 #define MCR_AFE_VAL(x) (((x) << MCR_AFE_SHIFT) & MCR_AFE_MASK) #define MCR_LOOP_MASK 0x10 #define MCR_LOOP_SHIFT 0x4 #define MCR_LOOP_VAL(x) (((x) << MCR_LOOP_SHIFT) & MCR_LOOP_MASK) #define MCR_OUT2_MASK 0x8 #define MCR_OUT2_SHIFT 0x3 #define MCR_OUT2_VAL(x) (((x) << MCR_OUT2_SHIFT) & MCR_OUT2_MASK) #define MCR_OUT1_MASK 0x4 #define MCR_OUT1_SHIFT 0x2 #define MCR_OUT1_VAL(x) (((x) << MCR_OUT1_SHIFT) & MCR_OUT1_MASK) #define MCR_RTS_MASK 0x2 #define MCR_RTS_SHIFT 0x1 #define MCR_RTS_VAL(x) (((x) << MCR_RTS_SHIFT) & MCR_RTS_MASK) #define MCR_DTR_MASK 0x1 #define MCR_DTR_SHIFT 0x0 #define MCR_DTR_VAL(x) (((x) << MCR_DTR_SHIFT) & MCR_DTR_MASK) #define MCR_RSV_8_31_MASK 0xFFFFFF00 #define MCR_RSV_8_31_SHIFT 0x8 #define MCR_RSV_8_31_VAL(x) (((x) << MCR_RSV_8_31_SHIFT) & MCR_RSV_8_31_MASK) #define MSR_DCD_MASK 0x80 #define MSR_DCD_SHIFT 0x7 #define MSR_DCD_VAL(x) (((x) << MSR_DCD_SHIFT) & MSR_DCD_MASK) #define MSR_RI_MASK 0x40 #define MSR_RI_SHIFT 0x6 #define MSR_RI_VAL(x) (((x) << MSR_RI_SHIFT) & MSR_RI_MASK) #define MSR_DSR_MASK 0x20 #define MSR_DSR_SHIFT 0x5 #define MSR_DSR_VAL(x) (((x) << MSR_DSR_SHIFT) & MSR_DSR_MASK) #define MSR_CTS_MASK 0x10 #define MSR_CTS_SHIFT 0x4 #define MSR_CTS_VAL(x) (((x) << MSR_CTS_SHIFT) & MSR_CTS_MASK) #define MSR_DDCD_MASK 0x8 #define MSR_DDCD_SHIFT 0x3 #define MSR_DDCD_VAL(x) (((x) << MSR_DDCD_SHIFT) & MSR_DDCD_MASK) #define MSR_TERI_MASK 0x4 #define MSR_TERI_SHIFT 0x2 #define MSR_TERI_VAL(x) (((x) << MSR_TERI_SHIFT) & MSR_TERI_MASK) #define MSR_DDSR_MASK 0x2 #define MSR_DDSR_SHIFT 0x1 #define MSR_DDSR_VAL(x) (((x) << MSR_DDSR_SHIFT) & MSR_DDSR_MASK) #define MSR_DCTS_MASK 0x1 #define MSR_DCTS_SHIFT 0x0 #define MSR_DCTS_VAL(x) (((x) << MSR_DCTS_SHIFT) & MSR_DCTS_MASK) #define MSR_RSV_8_31_MASK 0xFFFFFF00 #define MSR_RSV_8_31_SHIFT 0x8 #define MSR_RSV_8_31_VAL(x) (((x) << MSR_RSV_8_31_SHIFT) & MSR_RSV_8_31_MASK) #define SCR_Scratchpad_MASK 0xFF #define SCR_Scratchpad_SHIFT 0x0 #define SCR_Scratchpad_VAL(x) (((x) << SCR_Scratchpad_SHIFT) & SCR_Scratchpad_MASK) #define SCR_RSV_8_31_MASK 0xFFFFFF00 #define SCR_RSV_8_31_SHIFT 0x8 #define SCR_RSV_8_31_VAL(x) (((x) << SCR_RSV_8_31_SHIFT) & SCR_RSV_8_31_MASK) static inline u_int32_t get_RX(void); static inline u_int8_t get_RX_RX(void); static inline u_int8_t mem_get_RX_RX(u_int32_t reg_val); static inline void mem_set_RX_RX(u_int32_t *reg_val, u_int8_t bit_val); static inline void set_TX(u_int32_t val); static inline void set_TX_TX(u_int8_t bit_val); static inline u_int8_t mem_get_TX_TX(u_int32_t reg_val); static inline void mem_set_TX_TX(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int32_t get_DLL(void); static inline void set_DLL(u_int32_t val); static inline u_int8_t get_DLL_DLL(void); static inline void set_DLL_DLL(u_int8_t bit_val); static inline u_int8_t mem_get_DLL_DLL(u_int32_t reg_val); static inline void mem_set_DLL_DLL(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int32_t get_DLM(void); static inline void set_DLM(u_int32_t val); static inline u_int8_t get_DLM_DLM(void); static inline void set_DLM_DLM(u_int8_t bit_val); static inline u_int8_t mem_get_DLM_DLM(u_int32_t reg_val); static inline void mem_set_DLM_DLM(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int32_t get_IER(void); static inline void set_IER(u_int32_t val); static inline u_int8_t get_IER_DMAE(void); static inline void set_IER_DMAE(u_int8_t bit_val); static inline u_int8_t mem_get_IER_DMAE(u_int32_t reg_val); static inline void mem_set_IER_DMAE(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IER_UUE(void); static inline void set_IER_UUE(u_int8_t bit_val); static inline u_int8_t mem_get_IER_UUE(u_int32_t reg_val); static inline void mem_set_IER_UUE(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IER_NRZE(void); static inline void set_IER_NRZE(u_int8_t bit_val); static inline u_int8_t mem_get_IER_NRZE(u_int32_t reg_val); static inline void mem_set_IER_NRZE(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IER_RTOIE(void); static inline void set_IER_RTOIE(u_int8_t bit_val); static inline u_int8_t mem_get_IER_RTOIE(u_int32_t reg_val); static inline void mem_set_IER_RTOIE(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IER_MSI(void); static inline void set_IER_MSI(u_int8_t bit_val); static inline u_int8_t mem_get_IER_MSI(u_int32_t reg_val); static inline void mem_set_IER_MSI(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IER_RLSI(void); static inline void set_IER_RLSI(u_int8_t bit_val); static inline u_int8_t mem_get_IER_RLSI(u_int32_t reg_val); static inline void mem_set_IER_RLSI(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IER_THRI(void); static inline void set_IER_THRI(u_int8_t bit_val); static inline u_int8_t mem_get_IER_THRI(u_int32_t reg_val); static inline void mem_set_IER_THRI(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IER_RDI(void); static inline void set_IER_RDI(u_int8_t bit_val); static inline u_int8_t mem_get_IER_RDI(u_int32_t reg_val); static inline void mem_set_IER_RDI(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int32_t get_IIR(void); static inline u_int8_t get_IIR_FIFOES(void); static inline u_int8_t mem_get_IIR_FIFOES(u_int32_t reg_val); static inline void mem_set_IIR_FIFOES(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IIR_EOC(void); static inline u_int8_t mem_get_IIR_EOC(u_int32_t reg_val); static inline void mem_set_IIR_EOC(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IIR_ABL(void); static inline u_int8_t mem_get_IIR_ABL(u_int32_t reg_val); static inline void mem_set_IIR_ABL(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IIR_TOD(void); static inline u_int8_t mem_get_IIR_TOD(u_int32_t reg_val); static inline void mem_set_IIR_TOD(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IIR_ID(void); static inline u_int8_t mem_get_IIR_ID(u_int32_t reg_val); static inline void mem_set_IIR_ID(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IIR_NO_INT(void); static inline u_int8_t mem_get_IIR_NO_INT(u_int32_t reg_val); static inline void mem_set_IIR_NO_INT(u_int32_t *reg_val, u_int8_t bit_val); static inline void set_FCR(u_int32_t val); static inline u_int8_t mem_get_FCR_TRIGGER_MASK(u_int32_t reg_val); static inline void mem_set_FCR_TRIGGER_MASK(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t mem_get_FCR_BUS(u_int32_t reg_val); static inline void mem_set_FCR_BUS(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t mem_get_FCR_TRAIL(u_int32_t reg_val); static inline void mem_set_FCR_TRAIL(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t mem_get_FCR_DMA_SELECT(u_int32_t reg_val); static inline void mem_set_FCR_DMA_SELECT(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t mem_get_FCR_CLEAR_XMIT(u_int32_t reg_val); static inline void mem_set_FCR_CLEAR_XMIT(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t mem_get_FCR_CLEAR_RCVR(u_int32_t reg_val); static inline void mem_set_FCR_CLEAR_RCVR(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t mem_get_FCR_ENABLE_FIFO(u_int32_t reg_val); static inline void mem_set_FCR_ENABLE_FIFO(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int32_t get_LCR(void); static inline void set_LCR(u_int32_t val); static inline u_int8_t get_LCR_DLAB(void); static inline void set_LCR_DLAB(u_int8_t bit_val); static inline u_int8_t mem_get_LCR_DLAB(u_int32_t reg_val); static inline void mem_set_LCR_DLAB(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_LCR_SBC(void); static inline void set_LCR_SBC(u_int8_t bit_val); static inline u_int8_t mem_get_LCR_SBC(u_int32_t reg_val); static inline void mem_set_LCR_SBC(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_LCR_SPAR(void); static inline void set_LCR_SPAR(u_int8_t bit_val); static inline u_int8_t mem_get_LCR_SPAR(u_int32_t reg_val); static inline void mem_set_LCR_SPAR(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_LCR_EPAR(void); static inline void set_LCR_EPAR(u_int8_t bit_val); static inline u_int8_t mem_get_LCR_EPAR(u_int32_t reg_val); static inline void mem_set_LCR_EPAR(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_LCR_PARITY(void); static inline void set_LCR_PARITY(u_int8_t bit_val); static inline u_int8_t mem_get_LCR_PARITY(u_int32_t reg_val); static inline void mem_set_LCR_PARITY(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_LCR_STOP(void); static inline void set_LCR_STOP(u_int8_t bit_val); static inline u_int8_t mem_get_LCR_STOP(u_int32_t reg_val); static inline void mem_set_LCR_STOP(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_LCR_WLS(void); static inline void set_LCR_WLS(u_int8_t bit_val); static inline u_int8_t mem_get_LCR_WLS(u_int32_t reg_val); static inline void mem_set_LCR_WLS(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int32_t get_LSR(void); static inline u_int8_t get_LSR_FIFOE(void); static inline u_int8_t mem_get_LSR_FIFOE(u_int32_t reg_val); static inline void mem_set_LSR_FIFOE(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_LSR_TEMT(void); static inline u_int8_t mem_get_LSR_TEMT(u_int32_t reg_val); static inline void mem_set_LSR_TEMT(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_LSR_THRE(void); static inline u_int8_t mem_get_LSR_THRE(u_int32_t reg_val); static inline void mem_set_LSR_THRE(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_LSR_BI(void); static inline u_int8_t mem_get_LSR_BI(u_int32_t reg_val); static inline void mem_set_LSR_BI(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_LSR_FE(void); static inline u_int8_t mem_get_LSR_FE(u_int32_t reg_val); static inline void mem_set_LSR_FE(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_LSR_PE(void); static inline u_int8_t mem_get_LSR_PE(u_int32_t reg_val); static inline void mem_set_LSR_PE(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_LSR_OE(void); static inline u_int8_t mem_get_LSR_OE(u_int32_t reg_val); static inline void mem_set_LSR_OE(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_LSR_DR(void); static inline u_int8_t mem_get_LSR_DR(u_int32_t reg_val); static inline void mem_set_LSR_DR(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int32_t get_MCR(void); static inline void set_MCR(u_int32_t val); static inline u_int8_t get_MCR_AFE(void); static inline void set_MCR_AFE(u_int8_t bit_val); static inline u_int8_t mem_get_MCR_AFE(u_int32_t reg_val); static inline void mem_set_MCR_AFE(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MCR_LOOP(void); static inline void set_MCR_LOOP(u_int8_t bit_val); static inline u_int8_t mem_get_MCR_LOOP(u_int32_t reg_val); static inline void mem_set_MCR_LOOP(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MCR_OUT2(void); static inline void set_MCR_OUT2(u_int8_t bit_val); static inline u_int8_t mem_get_MCR_OUT2(u_int32_t reg_val); static inline void mem_set_MCR_OUT2(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MCR_OUT1(void); static inline void set_MCR_OUT1(u_int8_t bit_val); static inline u_int8_t mem_get_MCR_OUT1(u_int32_t reg_val); static inline void mem_set_MCR_OUT1(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MCR_RTS(void); static inline void set_MCR_RTS(u_int8_t bit_val); static inline u_int8_t mem_get_MCR_RTS(u_int32_t reg_val); static inline void mem_set_MCR_RTS(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MCR_DTR(void); static inline void set_MCR_DTR(u_int8_t bit_val); static inline u_int8_t mem_get_MCR_DTR(u_int32_t reg_val); static inline void mem_set_MCR_DTR(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int32_t get_MSR(void); static inline u_int8_t get_MSR_DCD(void); static inline u_int8_t mem_get_MSR_DCD(u_int32_t reg_val); static inline void mem_set_MSR_DCD(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MSR_RI(void); static inline u_int8_t mem_get_MSR_RI(u_int32_t reg_val); static inline void mem_set_MSR_RI(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MSR_DSR(void); static inline u_int8_t mem_get_MSR_DSR(u_int32_t reg_val); static inline void mem_set_MSR_DSR(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MSR_CTS(void); static inline u_int8_t mem_get_MSR_CTS(u_int32_t reg_val); static inline void mem_set_MSR_CTS(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MSR_DDCD(void); static inline u_int8_t mem_get_MSR_DDCD(u_int32_t reg_val); static inline void mem_set_MSR_DDCD(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MSR_TERI(void); static inline u_int8_t mem_get_MSR_TERI(u_int32_t reg_val); static inline void mem_set_MSR_TERI(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MSR_DDSR(void); static inline u_int8_t mem_get_MSR_DDSR(u_int32_t reg_val); static inline void mem_set_MSR_DDSR(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MSR_DCTS(void); static inline u_int8_t mem_get_MSR_DCTS(u_int32_t reg_val); static inline void mem_set_MSR_DCTS(u_int32_t *reg_val, u_int8_t bit_val); static inline u_int32_t get_SCR(void); static inline void set_SCR(u_int32_t val); static inline u_int8_t get_SCR_Scratchpad(void); static inline void set_SCR_Scratchpad(u_int8_t bit_val); static inline u_int8_t mem_get_SCR_Scratchpad(u_int32_t reg_val); static inline void mem_set_SCR_Scratchpad(u_int32_t *reg_val, u_int8_t bit_val); /* raw register access */ static inline u_int32_t _raw_read_RX(void); static inline u_int32_t _raw_read_RX(void){ u_int32_t retval = 0; retval = *(volatile u_int32_t*)(0xF8100000 + 0); return retval; } static inline u_int8_t _raw_read_RX_RX(void); static inline u_int8_t _raw_read_RX_RX(void){ return (_raw_read_RX() & RX_RX_MASK) >> RX_RX_SHIFT; } static inline void _raw_write_TX(u_int32_t val); static inline void _raw_write_TX(u_int32_t val){ *(volatile u_int32_t*)(0xF8100000 + 0) = val; } static inline u_int32_t _raw_read_DLL(void); static inline u_int32_t _raw_read_DLL(void){ u_int32_t retval = 0; retval = *(volatile u_int32_t*)(0xF8100000 + 0); return retval; } static inline void _raw_write_DLL(u_int32_t val); static inline void _raw_write_DLL(u_int32_t val){ *(volatile u_int32_t*)(0xF8100000 + 0) = val; } static inline u_int8_t _raw_read_DLL_DLL(void); static inline u_int8_t _raw_read_DLL_DLL(void){ return (_raw_read_DLL() & DLL_DLL_MASK) >> DLL_DLL_SHIFT; } static inline u_int32_t _raw_read_DLM(void); static inline u_int32_t _raw_read_DLM(void){ u_int32_t retval = 0; retval = *(volatile u_int32_t*)(0xF8100000 + 4); return retval; } static inline void _raw_write_DLM(u_int32_t val); static inline void _raw_write_DLM(u_int32_t val){ *(volatile u_int32_t*)(0xF8100000 + 4) = val; } static inline u_int8_t _raw_read_DLM_DLM(void); static inline u_int8_t _raw_read_DLM_DLM(void){ return (_raw_read_DLM() & DLM_DLM_MASK) >> DLM_DLM_SHIFT; } static inline u_int32_t _raw_read_IER(void); static inline u_int32_t _raw_read_IER(void){ u_int32_t retval = 0; retval = *(volatile u_int32_t*)(0xF8100000 + 4); return retval; } static inline void _raw_write_IER(u_int32_t val); static inline void _raw_write_IER(u_int32_t val){ *(volatile u_int32_t*)(0xF8100000 + 4) = val; } static inline u_int8_t _raw_read_IER_DMAE(void); static inline u_int8_t _raw_read_IER_DMAE(void){ return (_raw_read_IER() & IER_DMAE_MASK) >> IER_DMAE_SHIFT; } static inline u_int8_t _raw_read_IER_UUE(void); static inline u_int8_t _raw_read_IER_UUE(void){ return (_raw_read_IER() & IER_UUE_MASK) >> IER_UUE_SHIFT; } static inline u_int8_t _raw_read_IER_NRZE(void); static inline u_int8_t _raw_read_IER_NRZE(void){ return (_raw_read_IER() & IER_NRZE_MASK) >> IER_NRZE_SHIFT; } static inline u_int8_t _raw_read_IER_RTOIE(void); static inline u_int8_t _raw_read_IER_RTOIE(void){ return (_raw_read_IER() & IER_RTOIE_MASK) >> IER_RTOIE_SHIFT; } static inline u_int8_t _raw_read_IER_MSI(void); static inline u_int8_t _raw_read_IER_MSI(void){ return (_raw_read_IER() & IER_MSI_MASK) >> IER_MSI_SHIFT; } static inline u_int8_t _raw_read_IER_RLSI(void); static inline u_int8_t _raw_read_IER_RLSI(void){ return (_raw_read_IER() & IER_RLSI_MASK) >> IER_RLSI_SHIFT; } static inline u_int8_t _raw_read_IER_THRI(void); static inline u_int8_t _raw_read_IER_THRI(void){ return (_raw_read_IER() & IER_THRI_MASK) >> IER_THRI_SHIFT; } static inline u_int8_t _raw_read_IER_RDI(void); static inline u_int8_t _raw_read_IER_RDI(void){ return (_raw_read_IER() & IER_RDI_MASK) >> IER_RDI_SHIFT; } static inline u_int32_t _raw_read_IIR(void); static inline u_int32_t _raw_read_IIR(void){ u_int32_t retval = 0; retval = *(volatile u_int32_t*)(0xF8100000 + 8); return retval; } static inline u_int8_t _raw_read_IIR_FIFOES(void); static inline u_int8_t _raw_read_IIR_FIFOES(void){ return (_raw_read_IIR() & IIR_FIFOES_MASK) >> IIR_FIFOES_SHIFT; } static inline u_int8_t _raw_read_IIR_EOC(void); static inline u_int8_t _raw_read_IIR_EOC(void){ return (_raw_read_IIR() & IIR_EOC_MASK) >> IIR_EOC_SHIFT; } static inline u_int8_t _raw_read_IIR_ABL(void); static inline u_int8_t _raw_read_IIR_ABL(void){ return (_raw_read_IIR() & IIR_ABL_MASK) >> IIR_ABL_SHIFT; } static inline u_int8_t _raw_read_IIR_TOD(void); static inline u_int8_t _raw_read_IIR_TOD(void){ return (_raw_read_IIR() & IIR_TOD_MASK) >> IIR_TOD_SHIFT; } static inline u_int8_t _raw_read_IIR_ID(void); static inline u_int8_t _raw_read_IIR_ID(void){ return (_raw_read_IIR() & IIR_ID_MASK) >> IIR_ID_SHIFT; } static inline u_int8_t _raw_read_IIR_NO_INT(void); static inline u_int8_t _raw_read_IIR_NO_INT(void){ return (_raw_read_IIR() & IIR_NO_INT_MASK) >> IIR_NO_INT_SHIFT; } static inline void _raw_write_FCR(u_int32_t val); static inline void _raw_write_FCR(u_int32_t val){ *(volatile u_int32_t*)(0xF8100000 + 8) = val; } static inline u_int32_t _raw_read_LCR(void); static inline u_int32_t _raw_read_LCR(void){ u_int32_t retval = 0; retval = *(volatile u_int32_t*)(0xF8100000 + 12); return retval; } static inline void _raw_write_LCR(u_int32_t val); static inline void _raw_write_LCR(u_int32_t val){ *(volatile u_int32_t*)(0xF8100000 + 12) = val; } static inline u_int8_t _raw_read_LCR_DLAB(void); static inline u_int8_t _raw_read_LCR_DLAB(void){ return (_raw_read_LCR() & LCR_DLAB_MASK) >> LCR_DLAB_SHIFT; } static inline u_int8_t _raw_read_LCR_SBC(void); static inline u_int8_t _raw_read_LCR_SBC(void){ return (_raw_read_LCR() & LCR_SBC_MASK) >> LCR_SBC_SHIFT; } static inline u_int8_t _raw_read_LCR_SPAR(void); static inline u_int8_t _raw_read_LCR_SPAR(void){ return (_raw_read_LCR() & LCR_SPAR_MASK) >> LCR_SPAR_SHIFT; } static inline u_int8_t _raw_read_LCR_EPAR(void); static inline u_int8_t _raw_read_LCR_EPAR(void){ return (_raw_read_LCR() & LCR_EPAR_MASK) >> LCR_EPAR_SHIFT; } static inline u_int8_t _raw_read_LCR_PARITY(void); static inline u_int8_t _raw_read_LCR_PARITY(void){ return (_raw_read_LCR() & LCR_PARITY_MASK) >> LCR_PARITY_SHIFT; } static inline u_int8_t _raw_read_LCR_STOP(void); static inline u_int8_t _raw_read_LCR_STOP(void){ return (_raw_read_LCR() & LCR_STOP_MASK) >> LCR_STOP_SHIFT; } static inline u_int8_t _raw_read_LCR_WLS(void); static inline u_int8_t _raw_read_LCR_WLS(void){ return (_raw_read_LCR() & LCR_WLS_MASK) >> LCR_WLS_SHIFT; } static inline u_int32_t _raw_read_LSR(void); static inline u_int32_t _raw_read_LSR(void){ u_int32_t retval = 0; retval = *(volatile u_int32_t*)(0xF8100000 + 20); return retval; } static inline u_int8_t _raw_read_LSR_FIFOE(void); static inline u_int8_t _raw_read_LSR_FIFOE(void){ return (_raw_read_LSR() & LSR_FIFOE_MASK) >> LSR_FIFOE_SHIFT; } static inline u_int8_t _raw_read_LSR_TEMT(void); static inline u_int8_t _raw_read_LSR_TEMT(void){ return (_raw_read_LSR() & LSR_TEMT_MASK) >> LSR_TEMT_SHIFT; } static inline u_int8_t _raw_read_LSR_THRE(void); static inline u_int8_t _raw_read_LSR_THRE(void){ return (_raw_read_LSR() & LSR_THRE_MASK) >> LSR_THRE_SHIFT; } static inline u_int8_t _raw_read_LSR_BI(void); static inline u_int8_t _raw_read_LSR_BI(void){ return (_raw_read_LSR() & LSR_BI_MASK) >> LSR_BI_SHIFT; } static inline u_int8_t _raw_read_LSR_FE(void); static inline u_int8_t _raw_read_LSR_FE(void){ return (_raw_read_LSR() & LSR_FE_MASK) >> LSR_FE_SHIFT; } static inline u_int8_t _raw_read_LSR_PE(void); static inline u_int8_t _raw_read_LSR_PE(void){ return (_raw_read_LSR() & LSR_PE_MASK) >> LSR_PE_SHIFT; } static inline u_int8_t _raw_read_LSR_OE(void); static inline u_int8_t _raw_read_LSR_OE(void){ return (_raw_read_LSR() & LSR_OE_MASK) >> LSR_OE_SHIFT; } static inline u_int8_t _raw_read_LSR_DR(void); static inline u_int8_t _raw_read_LSR_DR(void){ return (_raw_read_LSR() & LSR_DR_MASK) >> LSR_DR_SHIFT; } static inline u_int32_t _raw_read_MCR(void); static inline u_int32_t _raw_read_MCR(void){ u_int32_t retval = 0; retval = *(volatile u_int32_t*)(0xF8100000 + 16); return retval; } static inline void _raw_write_MCR(u_int32_t val); static inline void _raw_write_MCR(u_int32_t val){ *(volatile u_int32_t*)(0xF8100000 + 16) = val; } static inline u_int8_t _raw_read_MCR_AFE(void); static inline u_int8_t _raw_read_MCR_AFE(void){ return (_raw_read_MCR() & MCR_AFE_MASK) >> MCR_AFE_SHIFT; } static inline u_int8_t _raw_read_MCR_LOOP(void); static inline u_int8_t _raw_read_MCR_LOOP(void){ return (_raw_read_MCR() & MCR_LOOP_MASK) >> MCR_LOOP_SHIFT; } static inline u_int8_t _raw_read_MCR_OUT2(void); static inline u_int8_t _raw_read_MCR_OUT2(void){ return (_raw_read_MCR() & MCR_OUT2_MASK) >> MCR_OUT2_SHIFT; } static inline u_int8_t _raw_read_MCR_OUT1(void); static inline u_int8_t _raw_read_MCR_OUT1(void){ return (_raw_read_MCR() & MCR_OUT1_MASK) >> MCR_OUT1_SHIFT; } static inline u_int8_t _raw_read_MCR_RTS(void); static inline u_int8_t _raw_read_MCR_RTS(void){ return (_raw_read_MCR() & MCR_RTS_MASK) >> MCR_RTS_SHIFT; } static inline u_int8_t _raw_read_MCR_DTR(void); static inline u_int8_t _raw_read_MCR_DTR(void){ return (_raw_read_MCR() & MCR_DTR_MASK) >> MCR_DTR_SHIFT; } static inline u_int32_t _raw_read_MSR(void); static inline u_int32_t _raw_read_MSR(void){ u_int32_t retval = 0; retval = *(volatile u_int32_t*)(0xF8100000 + 16); return retval; } static inline u_int8_t _raw_read_MSR_DCD(void); static inline u_int8_t _raw_read_MSR_DCD(void){ return (_raw_read_MSR() & MSR_DCD_MASK) >> MSR_DCD_SHIFT; } static inline u_int8_t _raw_read_MSR_RI(void); static inline u_int8_t _raw_read_MSR_RI(void){ return (_raw_read_MSR() & MSR_RI_MASK) >> MSR_RI_SHIFT; } static inline u_int8_t _raw_read_MSR_DSR(void); static inline u_int8_t _raw_read_MSR_DSR(void){ return (_raw_read_MSR() & MSR_DSR_MASK) >> MSR_DSR_SHIFT; } static inline u_int8_t _raw_read_MSR_CTS(void); static inline u_int8_t _raw_read_MSR_CTS(void){ return (_raw_read_MSR() & MSR_CTS_MASK) >> MSR_CTS_SHIFT; } static inline u_int8_t _raw_read_MSR_DDCD(void); static inline u_int8_t _raw_read_MSR_DDCD(void){ return (_raw_read_MSR() & MSR_DDCD_MASK) >> MSR_DDCD_SHIFT; } static inline u_int8_t _raw_read_MSR_TERI(void); static inline u_int8_t _raw_read_MSR_TERI(void){ return (_raw_read_MSR() & MSR_TERI_MASK) >> MSR_TERI_SHIFT; } static inline u_int8_t _raw_read_MSR_DDSR(void); static inline u_int8_t _raw_read_MSR_DDSR(void){ return (_raw_read_MSR() & MSR_DDSR_MASK) >> MSR_DDSR_SHIFT; } static inline u_int8_t _raw_read_MSR_DCTS(void); static inline u_int8_t _raw_read_MSR_DCTS(void){ return (_raw_read_MSR() & MSR_DCTS_MASK) >> MSR_DCTS_SHIFT; } static inline u_int32_t _raw_read_SCR(void); static inline u_int32_t _raw_read_SCR(void){ u_int32_t retval = 0; retval = *(volatile u_int32_t*)(0xF8100000 + 28); return retval; } static inline void _raw_write_SCR(u_int32_t val); static inline void _raw_write_SCR(u_int32_t val){ *(volatile u_int32_t*)(0xF8100000 + 28) = val; } static inline u_int8_t _raw_read_SCR_Scratchpad(void); static inline u_int8_t _raw_read_SCR_Scratchpad(void){ return (_raw_read_SCR() & SCR_Scratchpad_MASK) >> SCR_Scratchpad_SHIFT; } /* accesing register RX (read only) */ static inline u_int32_t get_RX(void){ u_int32_t val; val = _raw_read_RX(); return val; } static inline u_int8_t get_RX_RX(void){ u_int32_t reg_val; reg_val = get_RX(); return (reg_val & RX_RX_MASK) >> RX_RX_SHIFT; } static inline u_int8_t mem_get_RX_RX(u_int32_t reg_val){ return (reg_val & RX_RX_MASK) >> RX_RX_SHIFT; } static inline void mem_set_RX_RX(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~RX_RX_MASK) | ((bit_val << RX_RX_SHIFT) & RX_RX_MASK); } /* accesing register TX (write only) */ static inline void set_TX(u_int32_t val){ _raw_write_TX(val); } static inline void set_TX_TX(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = (reg_val & ~TX_RSV_8_31_MASK) | ((0 << TX_RSV_8_31_SHIFT) & TX_RSV_8_31_MASK); reg_val = (reg_val & ~TX_TX_MASK) | ((bit_val << TX_TX_SHIFT) & TX_TX_MASK); set_TX(reg_val); } static inline u_int8_t mem_get_TX_TX(u_int32_t reg_val){ return (reg_val & TX_TX_MASK) >> TX_TX_SHIFT; } static inline void mem_set_TX_TX(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~TX_TX_MASK) | ((bit_val << TX_TX_SHIFT) & TX_TX_MASK); } /* accesing register DLL (read write) */ static inline u_int32_t get_DLL(void){ u_int32_t val; val = _raw_read_DLL(); return val; } static inline void set_DLL(u_int32_t val){ _raw_write_DLL(val); } static inline u_int8_t get_DLL_DLL(void){ u_int32_t reg_val; reg_val = get_DLL(); return (reg_val & DLL_DLL_MASK) >> DLL_DLL_SHIFT; } static inline void set_DLL_DLL(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = (reg_val & ~DLL_RSV_8_31_MASK) | ((0 << DLL_RSV_8_31_SHIFT) & DLL_RSV_8_31_MASK); reg_val = (reg_val & ~DLL_DLL_MASK) | ((bit_val << DLL_DLL_SHIFT) & DLL_DLL_MASK); set_DLL(reg_val); } static inline u_int8_t mem_get_DLL_DLL(u_int32_t reg_val){ return (reg_val & DLL_DLL_MASK) >> DLL_DLL_SHIFT; } static inline void mem_set_DLL_DLL(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~DLL_DLL_MASK) | ((bit_val << DLL_DLL_SHIFT) & DLL_DLL_MASK); } /* accesing register DLM (read write) */ static inline u_int32_t get_DLM(void){ u_int32_t val; val = _raw_read_DLM(); return val; } static inline void set_DLM(u_int32_t val){ _raw_write_DLM(val); } static inline u_int8_t get_DLM_DLM(void){ u_int32_t reg_val; reg_val = get_DLM(); return (reg_val & DLM_DLM_MASK) >> DLM_DLM_SHIFT; } static inline void set_DLM_DLM(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = (reg_val & ~DLM_RSV_8_31_MASK) | ((0 << DLM_RSV_8_31_SHIFT) & DLM_RSV_8_31_MASK); reg_val = (reg_val & ~DLM_DLM_MASK) | ((bit_val << DLM_DLM_SHIFT) & DLM_DLM_MASK); set_DLM(reg_val); } static inline u_int8_t mem_get_DLM_DLM(u_int32_t reg_val){ return (reg_val & DLM_DLM_MASK) >> DLM_DLM_SHIFT; } static inline void mem_set_DLM_DLM(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~DLM_DLM_MASK) | ((bit_val << DLM_DLM_SHIFT) & DLM_DLM_MASK); } /* accesing register IER (read write) */ static inline u_int32_t get_IER(void){ u_int32_t val; val = _raw_read_IER(); return val; } static inline void set_IER(u_int32_t val){ _raw_write_IER(val); } static inline u_int8_t get_IER_DMAE(void){ u_int32_t reg_val; reg_val = get_IER(); return (reg_val & IER_DMAE_MASK) >> IER_DMAE_SHIFT; } static inline void set_IER_DMAE(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_IER(); reg_val = (reg_val & ~IER_RSV_8_31_MASK) | ((0 << IER_RSV_8_31_SHIFT) & IER_RSV_8_31_MASK); reg_val = (reg_val & ~IER_DMAE_MASK) | ((bit_val << IER_DMAE_SHIFT) & IER_DMAE_MASK); set_IER(reg_val); } static inline u_int8_t mem_get_IER_DMAE(u_int32_t reg_val){ return (reg_val & IER_DMAE_MASK) >> IER_DMAE_SHIFT; } static inline void mem_set_IER_DMAE(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IER_DMAE_MASK) | ((bit_val << IER_DMAE_SHIFT) & IER_DMAE_MASK); } static inline u_int8_t get_IER_UUE(void){ u_int32_t reg_val; reg_val = get_IER(); return (reg_val & IER_UUE_MASK) >> IER_UUE_SHIFT; } static inline void set_IER_UUE(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_IER(); reg_val = (reg_val & ~IER_RSV_8_31_MASK) | ((0 << IER_RSV_8_31_SHIFT) & IER_RSV_8_31_MASK); reg_val = (reg_val & ~IER_UUE_MASK) | ((bit_val << IER_UUE_SHIFT) & IER_UUE_MASK); set_IER(reg_val); } static inline u_int8_t mem_get_IER_UUE(u_int32_t reg_val){ return (reg_val & IER_UUE_MASK) >> IER_UUE_SHIFT; } static inline void mem_set_IER_UUE(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IER_UUE_MASK) | ((bit_val << IER_UUE_SHIFT) & IER_UUE_MASK); } static inline u_int8_t get_IER_NRZE(void){ u_int32_t reg_val; reg_val = get_IER(); return (reg_val & IER_NRZE_MASK) >> IER_NRZE_SHIFT; } static inline void set_IER_NRZE(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_IER(); reg_val = (reg_val & ~IER_RSV_8_31_MASK) | ((0 << IER_RSV_8_31_SHIFT) & IER_RSV_8_31_MASK); reg_val = (reg_val & ~IER_NRZE_MASK) | ((bit_val << IER_NRZE_SHIFT) & IER_NRZE_MASK); set_IER(reg_val); } static inline u_int8_t mem_get_IER_NRZE(u_int32_t reg_val){ return (reg_val & IER_NRZE_MASK) >> IER_NRZE_SHIFT; } static inline void mem_set_IER_NRZE(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IER_NRZE_MASK) | ((bit_val << IER_NRZE_SHIFT) & IER_NRZE_MASK); } static inline u_int8_t get_IER_RTOIE(void){ u_int32_t reg_val; reg_val = get_IER(); return (reg_val & IER_RTOIE_MASK) >> IER_RTOIE_SHIFT; } static inline void set_IER_RTOIE(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_IER(); reg_val = (reg_val & ~IER_RSV_8_31_MASK) | ((0 << IER_RSV_8_31_SHIFT) & IER_RSV_8_31_MASK); reg_val = (reg_val & ~IER_RTOIE_MASK) | ((bit_val << IER_RTOIE_SHIFT) & IER_RTOIE_MASK); set_IER(reg_val); } static inline u_int8_t mem_get_IER_RTOIE(u_int32_t reg_val){ return (reg_val & IER_RTOIE_MASK) >> IER_RTOIE_SHIFT; } static inline void mem_set_IER_RTOIE(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IER_RTOIE_MASK) | ((bit_val << IER_RTOIE_SHIFT) & IER_RTOIE_MASK); } static inline u_int8_t get_IER_MSI(void){ u_int32_t reg_val; reg_val = get_IER(); return (reg_val & IER_MSI_MASK) >> IER_MSI_SHIFT; } static inline void set_IER_MSI(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_IER(); reg_val = (reg_val & ~IER_RSV_8_31_MASK) | ((0 << IER_RSV_8_31_SHIFT) & IER_RSV_8_31_MASK); reg_val = (reg_val & ~IER_MSI_MASK) | ((bit_val << IER_MSI_SHIFT) & IER_MSI_MASK); set_IER(reg_val); } static inline u_int8_t mem_get_IER_MSI(u_int32_t reg_val){ return (reg_val & IER_MSI_MASK) >> IER_MSI_SHIFT; } static inline void mem_set_IER_MSI(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IER_MSI_MASK) | ((bit_val << IER_MSI_SHIFT) & IER_MSI_MASK); } static inline u_int8_t get_IER_RLSI(void){ u_int32_t reg_val; reg_val = get_IER(); return (reg_val & IER_RLSI_MASK) >> IER_RLSI_SHIFT; } static inline void set_IER_RLSI(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_IER(); reg_val = (reg_val & ~IER_RSV_8_31_MASK) | ((0 << IER_RSV_8_31_SHIFT) & IER_RSV_8_31_MASK); reg_val = (reg_val & ~IER_RLSI_MASK) | ((bit_val << IER_RLSI_SHIFT) & IER_RLSI_MASK); set_IER(reg_val); } static inline u_int8_t mem_get_IER_RLSI(u_int32_t reg_val){ return (reg_val & IER_RLSI_MASK) >> IER_RLSI_SHIFT; } static inline void mem_set_IER_RLSI(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IER_RLSI_MASK) | ((bit_val << IER_RLSI_SHIFT) & IER_RLSI_MASK); } static inline u_int8_t get_IER_THRI(void){ u_int32_t reg_val; reg_val = get_IER(); return (reg_val & IER_THRI_MASK) >> IER_THRI_SHIFT; } static inline void set_IER_THRI(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_IER(); reg_val = (reg_val & ~IER_RSV_8_31_MASK) | ((0 << IER_RSV_8_31_SHIFT) & IER_RSV_8_31_MASK); reg_val = (reg_val & ~IER_THRI_MASK) | ((bit_val << IER_THRI_SHIFT) & IER_THRI_MASK); set_IER(reg_val); } static inline u_int8_t mem_get_IER_THRI(u_int32_t reg_val){ return (reg_val & IER_THRI_MASK) >> IER_THRI_SHIFT; } static inline void mem_set_IER_THRI(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IER_THRI_MASK) | ((bit_val << IER_THRI_SHIFT) & IER_THRI_MASK); } static inline u_int8_t get_IER_RDI(void){ u_int32_t reg_val; reg_val = get_IER(); return (reg_val & IER_RDI_MASK) >> IER_RDI_SHIFT; } static inline void set_IER_RDI(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_IER(); reg_val = (reg_val & ~IER_RSV_8_31_MASK) | ((0 << IER_RSV_8_31_SHIFT) & IER_RSV_8_31_MASK); reg_val = (reg_val & ~IER_RDI_MASK) | ((bit_val << IER_RDI_SHIFT) & IER_RDI_MASK); set_IER(reg_val); } static inline u_int8_t mem_get_IER_RDI(u_int32_t reg_val){ return (reg_val & IER_RDI_MASK) >> IER_RDI_SHIFT; } static inline void mem_set_IER_RDI(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IER_RDI_MASK) | ((bit_val << IER_RDI_SHIFT) & IER_RDI_MASK); } /* accesing register IIR (read only) */ static inline u_int32_t get_IIR(void){ u_int32_t val; val = _raw_read_IIR(); return val; } static inline u_int8_t get_IIR_FIFOES(void){ u_int32_t reg_val; reg_val = get_IIR(); return (reg_val & IIR_FIFOES_MASK) >> IIR_FIFOES_SHIFT; } static inline u_int8_t mem_get_IIR_FIFOES(u_int32_t reg_val){ return (reg_val & IIR_FIFOES_MASK) >> IIR_FIFOES_SHIFT; } static inline void mem_set_IIR_FIFOES(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IIR_FIFOES_MASK) | ((bit_val << IIR_FIFOES_SHIFT) & IIR_FIFOES_MASK); } static inline u_int8_t get_IIR_EOC(void){ u_int32_t reg_val; reg_val = get_IIR(); return (reg_val & IIR_EOC_MASK) >> IIR_EOC_SHIFT; } static inline u_int8_t mem_get_IIR_EOC(u_int32_t reg_val){ return (reg_val & IIR_EOC_MASK) >> IIR_EOC_SHIFT; } static inline void mem_set_IIR_EOC(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IIR_EOC_MASK) | ((bit_val << IIR_EOC_SHIFT) & IIR_EOC_MASK); } static inline u_int8_t get_IIR_ABL(void){ u_int32_t reg_val; reg_val = get_IIR(); return (reg_val & IIR_ABL_MASK) >> IIR_ABL_SHIFT; } static inline u_int8_t mem_get_IIR_ABL(u_int32_t reg_val){ return (reg_val & IIR_ABL_MASK) >> IIR_ABL_SHIFT; } static inline void mem_set_IIR_ABL(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IIR_ABL_MASK) | ((bit_val << IIR_ABL_SHIFT) & IIR_ABL_MASK); } static inline u_int8_t get_IIR_TOD(void){ u_int32_t reg_val; reg_val = get_IIR(); return (reg_val & IIR_TOD_MASK) >> IIR_TOD_SHIFT; } static inline u_int8_t mem_get_IIR_TOD(u_int32_t reg_val){ return (reg_val & IIR_TOD_MASK) >> IIR_TOD_SHIFT; } static inline void mem_set_IIR_TOD(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IIR_TOD_MASK) | ((bit_val << IIR_TOD_SHIFT) & IIR_TOD_MASK); } static inline u_int8_t get_IIR_ID(void){ u_int32_t reg_val; reg_val = get_IIR(); return (reg_val & IIR_ID_MASK) >> IIR_ID_SHIFT; } static inline u_int8_t mem_get_IIR_ID(u_int32_t reg_val){ return (reg_val & IIR_ID_MASK) >> IIR_ID_SHIFT; } static inline void mem_set_IIR_ID(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IIR_ID_MASK) | ((bit_val << IIR_ID_SHIFT) & IIR_ID_MASK); } static inline u_int8_t get_IIR_NO_INT(void){ u_int32_t reg_val; reg_val = get_IIR(); return (reg_val & IIR_NO_INT_MASK) >> IIR_NO_INT_SHIFT; } static inline u_int8_t mem_get_IIR_NO_INT(u_int32_t reg_val){ return (reg_val & IIR_NO_INT_MASK) >> IIR_NO_INT_SHIFT; } static inline void mem_set_IIR_NO_INT(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IIR_NO_INT_MASK) | ((bit_val << IIR_NO_INT_SHIFT) & IIR_NO_INT_MASK); } /* accesing register FCR (write only) */ static inline void set_FCR(u_int32_t val){ _raw_write_FCR(val); } /*TRIGGER_MASK skipped since other bits are explicit */ static inline u_int8_t mem_get_FCR_TRIGGER_MASK(u_int32_t reg_val){ return (reg_val & FCR_TRIGGER_MASK_MASK) >> FCR_TRIGGER_MASK_SHIFT; } static inline void mem_set_FCR_TRIGGER_MASK(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~FCR_TRIGGER_MASK_MASK) | ((bit_val << FCR_TRIGGER_MASK_SHIFT) & FCR_TRIGGER_MASK_MASK); } /*BUS skipped since other bits are explicit */ static inline u_int8_t mem_get_FCR_BUS(u_int32_t reg_val){ return (reg_val & FCR_BUS_MASK) >> FCR_BUS_SHIFT; } static inline void mem_set_FCR_BUS(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~FCR_BUS_MASK) | ((bit_val << FCR_BUS_SHIFT) & FCR_BUS_MASK); } /*TRAIL skipped since other bits are explicit */ static inline u_int8_t mem_get_FCR_TRAIL(u_int32_t reg_val){ return (reg_val & FCR_TRAIL_MASK) >> FCR_TRAIL_SHIFT; } static inline void mem_set_FCR_TRAIL(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~FCR_TRAIL_MASK) | ((bit_val << FCR_TRAIL_SHIFT) & FCR_TRAIL_MASK); } /*DMA_SELECT skipped since other bits are explicit */ static inline u_int8_t mem_get_FCR_DMA_SELECT(u_int32_t reg_val){ return (reg_val & FCR_DMA_SELECT_MASK) >> FCR_DMA_SELECT_SHIFT; } static inline void mem_set_FCR_DMA_SELECT(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~FCR_DMA_SELECT_MASK) | ((bit_val << FCR_DMA_SELECT_SHIFT) & FCR_DMA_SELECT_MASK); } /*CLEAR_XMIT skipped since other bits are explicit */ static inline u_int8_t mem_get_FCR_CLEAR_XMIT(u_int32_t reg_val){ return (reg_val & FCR_CLEAR_XMIT_MASK) >> FCR_CLEAR_XMIT_SHIFT; } static inline void mem_set_FCR_CLEAR_XMIT(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~FCR_CLEAR_XMIT_MASK) | ((bit_val << FCR_CLEAR_XMIT_SHIFT) & FCR_CLEAR_XMIT_MASK); } /*CLEAR_RCVR skipped since other bits are explicit */ static inline u_int8_t mem_get_FCR_CLEAR_RCVR(u_int32_t reg_val){ return (reg_val & FCR_CLEAR_RCVR_MASK) >> FCR_CLEAR_RCVR_SHIFT; } static inline void mem_set_FCR_CLEAR_RCVR(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~FCR_CLEAR_RCVR_MASK) | ((bit_val << FCR_CLEAR_RCVR_SHIFT) & FCR_CLEAR_RCVR_MASK); } /*ENABLE_FIFO skipped since other bits are explicit */ static inline u_int8_t mem_get_FCR_ENABLE_FIFO(u_int32_t reg_val){ return (reg_val & FCR_ENABLE_FIFO_MASK) >> FCR_ENABLE_FIFO_SHIFT; } static inline void mem_set_FCR_ENABLE_FIFO(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~FCR_ENABLE_FIFO_MASK) | ((bit_val << FCR_ENABLE_FIFO_SHIFT) & FCR_ENABLE_FIFO_MASK); } /* accesing register LCR (read write) */ static inline u_int32_t get_LCR(void){ u_int32_t val; val = _raw_read_LCR(); return val; } static inline void set_LCR(u_int32_t val){ _raw_write_LCR(val); } static inline u_int8_t get_LCR_DLAB(void){ u_int32_t reg_val; reg_val = get_LCR(); return (reg_val & LCR_DLAB_MASK) >> LCR_DLAB_SHIFT; } static inline void set_LCR_DLAB(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_LCR(); reg_val = (reg_val & ~LCR_RSV_8_31_MASK) | ((0 << LCR_RSV_8_31_SHIFT) & LCR_RSV_8_31_MASK); reg_val = (reg_val & ~LCR_DLAB_MASK) | ((bit_val << LCR_DLAB_SHIFT) & LCR_DLAB_MASK); set_LCR(reg_val); } static inline u_int8_t mem_get_LCR_DLAB(u_int32_t reg_val){ return (reg_val & LCR_DLAB_MASK) >> LCR_DLAB_SHIFT; } static inline void mem_set_LCR_DLAB(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~LCR_DLAB_MASK) | ((bit_val << LCR_DLAB_SHIFT) & LCR_DLAB_MASK); } static inline u_int8_t get_LCR_SBC(void){ u_int32_t reg_val; reg_val = get_LCR(); return (reg_val & LCR_SBC_MASK) >> LCR_SBC_SHIFT; } static inline void set_LCR_SBC(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_LCR(); reg_val = (reg_val & ~LCR_RSV_8_31_MASK) | ((0 << LCR_RSV_8_31_SHIFT) & LCR_RSV_8_31_MASK); reg_val = (reg_val & ~LCR_SBC_MASK) | ((bit_val << LCR_SBC_SHIFT) & LCR_SBC_MASK); set_LCR(reg_val); } static inline u_int8_t mem_get_LCR_SBC(u_int32_t reg_val){ return (reg_val & LCR_SBC_MASK) >> LCR_SBC_SHIFT; } static inline void mem_set_LCR_SBC(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~LCR_SBC_MASK) | ((bit_val << LCR_SBC_SHIFT) & LCR_SBC_MASK); } static inline u_int8_t get_LCR_SPAR(void){ u_int32_t reg_val; reg_val = get_LCR(); return (reg_val & LCR_SPAR_MASK) >> LCR_SPAR_SHIFT; } static inline void set_LCR_SPAR(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_LCR(); reg_val = (reg_val & ~LCR_RSV_8_31_MASK) | ((0 << LCR_RSV_8_31_SHIFT) & LCR_RSV_8_31_MASK); reg_val = (reg_val & ~LCR_SPAR_MASK) | ((bit_val << LCR_SPAR_SHIFT) & LCR_SPAR_MASK); set_LCR(reg_val); } static inline u_int8_t mem_get_LCR_SPAR(u_int32_t reg_val){ return (reg_val & LCR_SPAR_MASK) >> LCR_SPAR_SHIFT; } static inline void mem_set_LCR_SPAR(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~LCR_SPAR_MASK) | ((bit_val << LCR_SPAR_SHIFT) & LCR_SPAR_MASK); } static inline u_int8_t get_LCR_EPAR(void){ u_int32_t reg_val; reg_val = get_LCR(); return (reg_val & LCR_EPAR_MASK) >> LCR_EPAR_SHIFT; } static inline void set_LCR_EPAR(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_LCR(); reg_val = (reg_val & ~LCR_RSV_8_31_MASK) | ((0 << LCR_RSV_8_31_SHIFT) & LCR_RSV_8_31_MASK); reg_val = (reg_val & ~LCR_EPAR_MASK) | ((bit_val << LCR_EPAR_SHIFT) & LCR_EPAR_MASK); set_LCR(reg_val); } static inline u_int8_t mem_get_LCR_EPAR(u_int32_t reg_val){ return (reg_val & LCR_EPAR_MASK) >> LCR_EPAR_SHIFT; } static inline void mem_set_LCR_EPAR(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~LCR_EPAR_MASK) | ((bit_val << LCR_EPAR_SHIFT) & LCR_EPAR_MASK); } static inline u_int8_t get_LCR_PARITY(void){ u_int32_t reg_val; reg_val = get_LCR(); return (reg_val & LCR_PARITY_MASK) >> LCR_PARITY_SHIFT; } static inline void set_LCR_PARITY(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_LCR(); reg_val = (reg_val & ~LCR_RSV_8_31_MASK) | ((0 << LCR_RSV_8_31_SHIFT) & LCR_RSV_8_31_MASK); reg_val = (reg_val & ~LCR_PARITY_MASK) | ((bit_val << LCR_PARITY_SHIFT) & LCR_PARITY_MASK); set_LCR(reg_val); } static inline u_int8_t mem_get_LCR_PARITY(u_int32_t reg_val){ return (reg_val & LCR_PARITY_MASK) >> LCR_PARITY_SHIFT; } static inline void mem_set_LCR_PARITY(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~LCR_PARITY_MASK) | ((bit_val << LCR_PARITY_SHIFT) & LCR_PARITY_MASK); } static inline u_int8_t get_LCR_STOP(void){ u_int32_t reg_val; reg_val = get_LCR(); return (reg_val & LCR_STOP_MASK) >> LCR_STOP_SHIFT; } static inline void set_LCR_STOP(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_LCR(); reg_val = (reg_val & ~LCR_RSV_8_31_MASK) | ((0 << LCR_RSV_8_31_SHIFT) & LCR_RSV_8_31_MASK); reg_val = (reg_val & ~LCR_STOP_MASK) | ((bit_val << LCR_STOP_SHIFT) & LCR_STOP_MASK); set_LCR(reg_val); } static inline u_int8_t mem_get_LCR_STOP(u_int32_t reg_val){ return (reg_val & LCR_STOP_MASK) >> LCR_STOP_SHIFT; } static inline void mem_set_LCR_STOP(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~LCR_STOP_MASK) | ((bit_val << LCR_STOP_SHIFT) & LCR_STOP_MASK); } static inline u_int8_t get_LCR_WLS(void){ u_int32_t reg_val; reg_val = get_LCR(); return (reg_val & LCR_WLS_MASK) >> LCR_WLS_SHIFT; } static inline void set_LCR_WLS(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_LCR(); reg_val = (reg_val & ~LCR_RSV_8_31_MASK) | ((0 << LCR_RSV_8_31_SHIFT) & LCR_RSV_8_31_MASK); reg_val = (reg_val & ~LCR_WLS_MASK) | ((bit_val << LCR_WLS_SHIFT) & LCR_WLS_MASK); set_LCR(reg_val); } static inline u_int8_t mem_get_LCR_WLS(u_int32_t reg_val){ return (reg_val & LCR_WLS_MASK) >> LCR_WLS_SHIFT; } static inline void mem_set_LCR_WLS(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~LCR_WLS_MASK) | ((bit_val << LCR_WLS_SHIFT) & LCR_WLS_MASK); } /* accesing register LSR (read only) */ static inline u_int32_t get_LSR(void){ u_int32_t val; val = _raw_read_LSR(); return val; } static inline u_int8_t get_LSR_FIFOE(void){ u_int32_t reg_val; reg_val = get_LSR(); return (reg_val & LSR_FIFOE_MASK) >> LSR_FIFOE_SHIFT; } static inline u_int8_t mem_get_LSR_FIFOE(u_int32_t reg_val){ return (reg_val & LSR_FIFOE_MASK) >> LSR_FIFOE_SHIFT; } static inline void mem_set_LSR_FIFOE(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~LSR_FIFOE_MASK) | ((bit_val << LSR_FIFOE_SHIFT) & LSR_FIFOE_MASK); } static inline u_int8_t get_LSR_TEMT(void){ u_int32_t reg_val; reg_val = get_LSR(); return (reg_val & LSR_TEMT_MASK) >> LSR_TEMT_SHIFT; } static inline u_int8_t mem_get_LSR_TEMT(u_int32_t reg_val){ return (reg_val & LSR_TEMT_MASK) >> LSR_TEMT_SHIFT; } static inline void mem_set_LSR_TEMT(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~LSR_TEMT_MASK) | ((bit_val << LSR_TEMT_SHIFT) & LSR_TEMT_MASK); } static inline u_int8_t get_LSR_THRE(void){ u_int32_t reg_val; reg_val = get_LSR(); return (reg_val & LSR_THRE_MASK) >> LSR_THRE_SHIFT; } static inline u_int8_t mem_get_LSR_THRE(u_int32_t reg_val){ return (reg_val & LSR_THRE_MASK) >> LSR_THRE_SHIFT; } static inline void mem_set_LSR_THRE(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~LSR_THRE_MASK) | ((bit_val << LSR_THRE_SHIFT) & LSR_THRE_MASK); } static inline u_int8_t get_LSR_BI(void){ u_int32_t reg_val; reg_val = get_LSR(); return (reg_val & LSR_BI_MASK) >> LSR_BI_SHIFT; } static inline u_int8_t mem_get_LSR_BI(u_int32_t reg_val){ return (reg_val & LSR_BI_MASK) >> LSR_BI_SHIFT; } static inline void mem_set_LSR_BI(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~LSR_BI_MASK) | ((bit_val << LSR_BI_SHIFT) & LSR_BI_MASK); } static inline u_int8_t get_LSR_FE(void){ u_int32_t reg_val; reg_val = get_LSR(); return (reg_val & LSR_FE_MASK) >> LSR_FE_SHIFT; } static inline u_int8_t mem_get_LSR_FE(u_int32_t reg_val){ return (reg_val & LSR_FE_MASK) >> LSR_FE_SHIFT; } static inline void mem_set_LSR_FE(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~LSR_FE_MASK) | ((bit_val << LSR_FE_SHIFT) & LSR_FE_MASK); } static inline u_int8_t get_LSR_PE(void){ u_int32_t reg_val; reg_val = get_LSR(); return (reg_val & LSR_PE_MASK) >> LSR_PE_SHIFT; } static inline u_int8_t mem_get_LSR_PE(u_int32_t reg_val){ return (reg_val & LSR_PE_MASK) >> LSR_PE_SHIFT; } static inline void mem_set_LSR_PE(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~LSR_PE_MASK) | ((bit_val << LSR_PE_SHIFT) & LSR_PE_MASK); } static inline u_int8_t get_LSR_OE(void){ u_int32_t reg_val; reg_val = get_LSR(); return (reg_val & LSR_OE_MASK) >> LSR_OE_SHIFT; } static inline u_int8_t mem_get_LSR_OE(u_int32_t reg_val){ return (reg_val & LSR_OE_MASK) >> LSR_OE_SHIFT; } static inline void mem_set_LSR_OE(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~LSR_OE_MASK) | ((bit_val << LSR_OE_SHIFT) & LSR_OE_MASK); } static inline u_int8_t get_LSR_DR(void){ u_int32_t reg_val; reg_val = get_LSR(); return (reg_val & LSR_DR_MASK) >> LSR_DR_SHIFT; } static inline u_int8_t mem_get_LSR_DR(u_int32_t reg_val){ return (reg_val & LSR_DR_MASK) >> LSR_DR_SHIFT; } static inline void mem_set_LSR_DR(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~LSR_DR_MASK) | ((bit_val << LSR_DR_SHIFT) & LSR_DR_MASK); } /* accesing register MCR (read write) */ static inline u_int32_t get_MCR(void){ u_int32_t val; val = _raw_read_MCR(); return val; } static inline void set_MCR(u_int32_t val){ _raw_write_MCR(val); } static inline u_int8_t get_MCR_AFE(void){ u_int32_t reg_val; reg_val = get_MCR(); return (reg_val & MCR_AFE_MASK) >> MCR_AFE_SHIFT; } static inline void set_MCR_AFE(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_MCR(); reg_val = (reg_val & ~MCR_RSV_6_31_MASK) | ((0 << MCR_RSV_6_31_SHIFT) & MCR_RSV_6_31_MASK); reg_val = (reg_val & ~MCR_RSV_8_31_MASK) | ((0 << MCR_RSV_8_31_SHIFT) & MCR_RSV_8_31_MASK); reg_val = (reg_val & ~MCR_AFE_MASK) | ((bit_val << MCR_AFE_SHIFT) & MCR_AFE_MASK); set_MCR(reg_val); } static inline u_int8_t mem_get_MCR_AFE(u_int32_t reg_val){ return (reg_val & MCR_AFE_MASK) >> MCR_AFE_SHIFT; } static inline void mem_set_MCR_AFE(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MCR_AFE_MASK) | ((bit_val << MCR_AFE_SHIFT) & MCR_AFE_MASK); } static inline u_int8_t get_MCR_LOOP(void){ u_int32_t reg_val; reg_val = get_MCR(); return (reg_val & MCR_LOOP_MASK) >> MCR_LOOP_SHIFT; } static inline void set_MCR_LOOP(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_MCR(); reg_val = (reg_val & ~MCR_RSV_6_31_MASK) | ((0 << MCR_RSV_6_31_SHIFT) & MCR_RSV_6_31_MASK); reg_val = (reg_val & ~MCR_RSV_8_31_MASK) | ((0 << MCR_RSV_8_31_SHIFT) & MCR_RSV_8_31_MASK); reg_val = (reg_val & ~MCR_LOOP_MASK) | ((bit_val << MCR_LOOP_SHIFT) & MCR_LOOP_MASK); set_MCR(reg_val); } static inline u_int8_t mem_get_MCR_LOOP(u_int32_t reg_val){ return (reg_val & MCR_LOOP_MASK) >> MCR_LOOP_SHIFT; } static inline void mem_set_MCR_LOOP(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MCR_LOOP_MASK) | ((bit_val << MCR_LOOP_SHIFT) & MCR_LOOP_MASK); } static inline u_int8_t get_MCR_OUT2(void){ u_int32_t reg_val; reg_val = get_MCR(); return (reg_val & MCR_OUT2_MASK) >> MCR_OUT2_SHIFT; } static inline void set_MCR_OUT2(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_MCR(); reg_val = (reg_val & ~MCR_RSV_6_31_MASK) | ((0 << MCR_RSV_6_31_SHIFT) & MCR_RSV_6_31_MASK); reg_val = (reg_val & ~MCR_RSV_8_31_MASK) | ((0 << MCR_RSV_8_31_SHIFT) & MCR_RSV_8_31_MASK); reg_val = (reg_val & ~MCR_OUT2_MASK) | ((bit_val << MCR_OUT2_SHIFT) & MCR_OUT2_MASK); set_MCR(reg_val); } static inline u_int8_t mem_get_MCR_OUT2(u_int32_t reg_val){ return (reg_val & MCR_OUT2_MASK) >> MCR_OUT2_SHIFT; } static inline void mem_set_MCR_OUT2(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MCR_OUT2_MASK) | ((bit_val << MCR_OUT2_SHIFT) & MCR_OUT2_MASK); } static inline u_int8_t get_MCR_OUT1(void){ u_int32_t reg_val; reg_val = get_MCR(); return (reg_val & MCR_OUT1_MASK) >> MCR_OUT1_SHIFT; } static inline void set_MCR_OUT1(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_MCR(); reg_val = (reg_val & ~MCR_RSV_6_31_MASK) | ((0 << MCR_RSV_6_31_SHIFT) & MCR_RSV_6_31_MASK); reg_val = (reg_val & ~MCR_RSV_8_31_MASK) | ((0 << MCR_RSV_8_31_SHIFT) & MCR_RSV_8_31_MASK); reg_val = (reg_val & ~MCR_OUT1_MASK) | ((bit_val << MCR_OUT1_SHIFT) & MCR_OUT1_MASK); set_MCR(reg_val); } static inline u_int8_t mem_get_MCR_OUT1(u_int32_t reg_val){ return (reg_val & MCR_OUT1_MASK) >> MCR_OUT1_SHIFT; } static inline void mem_set_MCR_OUT1(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MCR_OUT1_MASK) | ((bit_val << MCR_OUT1_SHIFT) & MCR_OUT1_MASK); } static inline u_int8_t get_MCR_RTS(void){ u_int32_t reg_val; reg_val = get_MCR(); return (reg_val & MCR_RTS_MASK) >> MCR_RTS_SHIFT; } static inline void set_MCR_RTS(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_MCR(); reg_val = (reg_val & ~MCR_RSV_6_31_MASK) | ((0 << MCR_RSV_6_31_SHIFT) & MCR_RSV_6_31_MASK); reg_val = (reg_val & ~MCR_RSV_8_31_MASK) | ((0 << MCR_RSV_8_31_SHIFT) & MCR_RSV_8_31_MASK); reg_val = (reg_val & ~MCR_RTS_MASK) | ((bit_val << MCR_RTS_SHIFT) & MCR_RTS_MASK); set_MCR(reg_val); } static inline u_int8_t mem_get_MCR_RTS(u_int32_t reg_val){ return (reg_val & MCR_RTS_MASK) >> MCR_RTS_SHIFT; } static inline void mem_set_MCR_RTS(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MCR_RTS_MASK) | ((bit_val << MCR_RTS_SHIFT) & MCR_RTS_MASK); } static inline u_int8_t get_MCR_DTR(void){ u_int32_t reg_val; reg_val = get_MCR(); return (reg_val & MCR_DTR_MASK) >> MCR_DTR_SHIFT; } static inline void set_MCR_DTR(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = get_MCR(); reg_val = (reg_val & ~MCR_RSV_6_31_MASK) | ((0 << MCR_RSV_6_31_SHIFT) & MCR_RSV_6_31_MASK); reg_val = (reg_val & ~MCR_RSV_8_31_MASK) | ((0 << MCR_RSV_8_31_SHIFT) & MCR_RSV_8_31_MASK); reg_val = (reg_val & ~MCR_DTR_MASK) | ((bit_val << MCR_DTR_SHIFT) & MCR_DTR_MASK); set_MCR(reg_val); } static inline u_int8_t mem_get_MCR_DTR(u_int32_t reg_val){ return (reg_val & MCR_DTR_MASK) >> MCR_DTR_SHIFT; } static inline void mem_set_MCR_DTR(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MCR_DTR_MASK) | ((bit_val << MCR_DTR_SHIFT) & MCR_DTR_MASK); } /* accesing register MSR (read only) */ static inline u_int32_t get_MSR(void){ u_int32_t val; val = _raw_read_MSR(); return val; } static inline u_int8_t get_MSR_DCD(void){ u_int32_t reg_val; reg_val = get_MSR(); return (reg_val & MSR_DCD_MASK) >> MSR_DCD_SHIFT; } static inline u_int8_t mem_get_MSR_DCD(u_int32_t reg_val){ return (reg_val & MSR_DCD_MASK) >> MSR_DCD_SHIFT; } static inline void mem_set_MSR_DCD(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MSR_DCD_MASK) | ((bit_val << MSR_DCD_SHIFT) & MSR_DCD_MASK); } static inline u_int8_t get_MSR_RI(void){ u_int32_t reg_val; reg_val = get_MSR(); return (reg_val & MSR_RI_MASK) >> MSR_RI_SHIFT; } static inline u_int8_t mem_get_MSR_RI(u_int32_t reg_val){ return (reg_val & MSR_RI_MASK) >> MSR_RI_SHIFT; } static inline void mem_set_MSR_RI(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MSR_RI_MASK) | ((bit_val << MSR_RI_SHIFT) & MSR_RI_MASK); } static inline u_int8_t get_MSR_DSR(void){ u_int32_t reg_val; reg_val = get_MSR(); return (reg_val & MSR_DSR_MASK) >> MSR_DSR_SHIFT; } static inline u_int8_t mem_get_MSR_DSR(u_int32_t reg_val){ return (reg_val & MSR_DSR_MASK) >> MSR_DSR_SHIFT; } static inline void mem_set_MSR_DSR(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MSR_DSR_MASK) | ((bit_val << MSR_DSR_SHIFT) & MSR_DSR_MASK); } static inline u_int8_t get_MSR_CTS(void){ u_int32_t reg_val; reg_val = get_MSR(); return (reg_val & MSR_CTS_MASK) >> MSR_CTS_SHIFT; } static inline u_int8_t mem_get_MSR_CTS(u_int32_t reg_val){ return (reg_val & MSR_CTS_MASK) >> MSR_CTS_SHIFT; } static inline void mem_set_MSR_CTS(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MSR_CTS_MASK) | ((bit_val << MSR_CTS_SHIFT) & MSR_CTS_MASK); } static inline u_int8_t get_MSR_DDCD(void){ u_int32_t reg_val; reg_val = get_MSR(); return (reg_val & MSR_DDCD_MASK) >> MSR_DDCD_SHIFT; } static inline u_int8_t mem_get_MSR_DDCD(u_int32_t reg_val){ return (reg_val & MSR_DDCD_MASK) >> MSR_DDCD_SHIFT; } static inline void mem_set_MSR_DDCD(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MSR_DDCD_MASK) | ((bit_val << MSR_DDCD_SHIFT) & MSR_DDCD_MASK); } static inline u_int8_t get_MSR_TERI(void){ u_int32_t reg_val; reg_val = get_MSR(); return (reg_val & MSR_TERI_MASK) >> MSR_TERI_SHIFT; } static inline u_int8_t mem_get_MSR_TERI(u_int32_t reg_val){ return (reg_val & MSR_TERI_MASK) >> MSR_TERI_SHIFT; } static inline void mem_set_MSR_TERI(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MSR_TERI_MASK) | ((bit_val << MSR_TERI_SHIFT) & MSR_TERI_MASK); } static inline u_int8_t get_MSR_DDSR(void){ u_int32_t reg_val; reg_val = get_MSR(); return (reg_val & MSR_DDSR_MASK) >> MSR_DDSR_SHIFT; } static inline u_int8_t mem_get_MSR_DDSR(u_int32_t reg_val){ return (reg_val & MSR_DDSR_MASK) >> MSR_DDSR_SHIFT; } static inline void mem_set_MSR_DDSR(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MSR_DDSR_MASK) | ((bit_val << MSR_DDSR_SHIFT) & MSR_DDSR_MASK); } static inline u_int8_t get_MSR_DCTS(void){ u_int32_t reg_val; reg_val = get_MSR(); return (reg_val & MSR_DCTS_MASK) >> MSR_DCTS_SHIFT; } static inline u_int8_t mem_get_MSR_DCTS(u_int32_t reg_val){ return (reg_val & MSR_DCTS_MASK) >> MSR_DCTS_SHIFT; } static inline void mem_set_MSR_DCTS(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MSR_DCTS_MASK) | ((bit_val << MSR_DCTS_SHIFT) & MSR_DCTS_MASK); } /* accesing register SCR (read write) */ static inline u_int32_t get_SCR(void){ u_int32_t val; val = _raw_read_SCR(); return val; } static inline void set_SCR(u_int32_t val){ _raw_write_SCR(val); } static inline u_int8_t get_SCR_Scratchpad(void){ u_int32_t reg_val; reg_val = get_SCR(); return (reg_val & SCR_Scratchpad_MASK) >> SCR_Scratchpad_SHIFT; } static inline void set_SCR_Scratchpad(u_int8_t bit_val){ u_int32_t reg_val = 0; reg_val = (reg_val & ~SCR_RSV_8_31_MASK) | ((0 << SCR_RSV_8_31_SHIFT) & SCR_RSV_8_31_MASK); reg_val = (reg_val & ~SCR_Scratchpad_MASK) | ((bit_val << SCR_Scratchpad_SHIFT) & SCR_Scratchpad_MASK); set_SCR(reg_val); } static inline u_int8_t mem_get_SCR_Scratchpad(u_int32_t reg_val){ return (reg_val & SCR_Scratchpad_MASK) >> SCR_Scratchpad_SHIFT; } static inline void mem_set_SCR_Scratchpad(u_int32_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~SCR_Scratchpad_MASK) | ((bit_val << SCR_Scratchpad_SHIFT) & SCR_Scratchpad_MASK); }