#include "hail-os-dep.h" /* macros for mask and shift */ #define BSR_ID_MASK 0xFF00 #define BSR_ID_SHIFT 0x8 #define BSR_ID_VAL(x) (((x) << BSR_ID_SHIFT) & BSR_ID_MASK) #define BSR_RSV_3_7_MASK 0xF8 #define BSR_RSV_3_7_SHIFT 0x3 #define BSR_RSV_3_7_VAL(x) (((x) << BSR_RSV_3_7_SHIFT) & BSR_RSV_3_7_MASK) #define BSR_BANK_MASK 0x7 #define BSR_BANK_SHIFT 0x0 #define BSR_BANK_VAL(x) (((x) << BSR_BANK_SHIFT) & BSR_BANK_MASK) #define TCR_SWFDUP_MASK 0x8000 #define TCR_SWFDUP_SHIFT 0xF #define TCR_SWFDUP_VAL(x) (((x) << TCR_SWFDUP_SHIFT) & TCR_SWFDUP_MASK) #define TCR_RSV_14_14_MASK 0x4000 #define TCR_RSV_14_14_SHIFT 0xE #define TCR_RSV_14_14_VAL(x) (((x) << TCR_RSV_14_14_SHIFT) & TCR_RSV_14_14_MASK) #define TCR_EPH_LOOP_MASK 0x2000 #define TCR_EPH_LOOP_SHIFT 0xD #define TCR_EPH_LOOP_VAL(x) (((x) << TCR_EPH_LOOP_SHIFT) & TCR_EPH_LOOP_MASK) #define TCR_STP_SQET_MASK 0x1000 #define TCR_STP_SQET_SHIFT 0xC #define TCR_STP_SQET_VAL(x) (((x) << TCR_STP_SQET_SHIFT) & TCR_STP_SQET_MASK) #define TCR_FDUPLX_MASK 0x800 #define TCR_FDUPLX_SHIFT 0xB #define TCR_FDUPLX_VAL(x) (((x) << TCR_FDUPLX_SHIFT) & TCR_FDUPLX_MASK) #define TCR_MON_CSN_MASK 0x400 #define TCR_MON_CSN_SHIFT 0xA #define TCR_MON_CSN_VAL(x) (((x) << TCR_MON_CSN_SHIFT) & TCR_MON_CSN_MASK) #define TCR_RSV_9_9_MASK 0x200 #define TCR_RSV_9_9_SHIFT 0x9 #define TCR_RSV_9_9_VAL(x) (((x) << TCR_RSV_9_9_SHIFT) & TCR_RSV_9_9_MASK) #define TCR_NOCRC_MASK 0x100 #define TCR_NOCRC_SHIFT 0x8 #define TCR_NOCRC_VAL(x) (((x) << TCR_NOCRC_SHIFT) & TCR_NOCRC_MASK) #define TCR_PAD_EN_MASK 0x80 #define TCR_PAD_EN_SHIFT 0x7 #define TCR_PAD_EN_VAL(x) (((x) << TCR_PAD_EN_SHIFT) & TCR_PAD_EN_MASK) #define TCR_RSV_6_6_MASK 0x40 #define TCR_RSV_6_6_SHIFT 0x6 #define TCR_RSV_6_6_VAL(x) (((x) << TCR_RSV_6_6_SHIFT) & TCR_RSV_6_6_MASK) #define TCR_RSV_5_5_MASK 0x20 #define TCR_RSV_5_5_SHIFT 0x5 #define TCR_RSV_5_5_VAL(x) (((x) << TCR_RSV_5_5_SHIFT) & TCR_RSV_5_5_MASK) #define TCR_RSV_4_4_MASK 0x10 #define TCR_RSV_4_4_SHIFT 0x4 #define TCR_RSV_4_4_VAL(x) (((x) << TCR_RSV_4_4_SHIFT) & TCR_RSV_4_4_MASK) #define TCR_RSV_3_3_MASK 0x8 #define TCR_RSV_3_3_SHIFT 0x3 #define TCR_RSV_3_3_VAL(x) (((x) << TCR_RSV_3_3_SHIFT) & TCR_RSV_3_3_MASK) #define TCR_FORCOL_MASK 0x4 #define TCR_FORCOL_SHIFT 0x2 #define TCR_FORCOL_VAL(x) (((x) << TCR_FORCOL_SHIFT) & TCR_FORCOL_MASK) #define TCR_LOOP_MASK 0x2 #define TCR_LOOP_SHIFT 0x1 #define TCR_LOOP_VAL(x) (((x) << TCR_LOOP_SHIFT) & TCR_LOOP_MASK) #define TCR_TXENA_MASK 0x1 #define TCR_TXENA_SHIFT 0x0 #define TCR_TXENA_VAL(x) (((x) << TCR_TXENA_SHIFT) & TCR_TXENA_MASK) #define EPHSR_TX_UNRN_MASK 0x8000 #define EPHSR_TX_UNRN_SHIFT 0xF #define EPHSR_TX_UNRN_VAL(x) (((x) << EPHSR_TX_UNRN_SHIFT) & EPHSR_TX_UNRN_MASK) #define EPHSR_LINK_OK_MASK 0x4000 #define EPHSR_LINK_OK_SHIFT 0xE #define EPHSR_LINK_OK_VAL(x) (((x) << EPHSR_LINK_OK_SHIFT) & EPHSR_LINK_OK_MASK) #define EPHSR_RSV_13_13_MASK 0x2000 #define EPHSR_RSV_13_13_SHIFT 0xD #define EPHSR_RSV_13_13_VAL(x) (((x) << EPHSR_RSV_13_13_SHIFT) & EPHSR_RSV_13_13_MASK) #define EPHSR_CTR_ROL_MASK 0x1000 #define EPHSR_CTR_ROL_SHIFT 0xC #define EPHSR_CTR_ROL_VAL(x) (((x) << EPHSR_CTR_ROL_SHIFT) & EPHSR_CTR_ROL_MASK) #define EPHSR_EXC_DEF_MASK 0x800 #define EPHSR_EXC_DEF_SHIFT 0xB #define EPHSR_EXC_DEF_VAL(x) (((x) << EPHSR_EXC_DEF_SHIFT) & EPHSR_EXC_DEF_MASK) #define EPHSR_LOST_CAR_MASK 0x400 #define EPHSR_LOST_CAR_SHIFT 0xA #define EPHSR_LOST_CAR_VAL(x) (((x) << EPHSR_LOST_CAR_SHIFT) & EPHSR_LOST_CAR_MASK) #define EPHSR_LATCOL_MASK 0x200 #define EPHSR_LATCOL_SHIFT 0x9 #define EPHSR_LATCOL_VAL(x) (((x) << EPHSR_LATCOL_SHIFT) & EPHSR_LATCOL_MASK) #define EPHSR_RSV_8_8_MASK 0x100 #define EPHSR_RSV_8_8_SHIFT 0x8 #define EPHSR_RSV_8_8_VAL(x) (((x) << EPHSR_RSV_8_8_SHIFT) & EPHSR_RSV_8_8_MASK) #define EPHSR_TX_DEFR_MASK 0x80 #define EPHSR_TX_DEFR_SHIFT 0x7 #define EPHSR_TX_DEFR_VAL(x) (((x) << EPHSR_TX_DEFR_SHIFT) & EPHSR_TX_DEFR_MASK) #define EPHSR_LTX_BRD_MASK 0x40 #define EPHSR_LTX_BRD_SHIFT 0x6 #define EPHSR_LTX_BRD_VAL(x) (((x) << EPHSR_LTX_BRD_SHIFT) & EPHSR_LTX_BRD_MASK) #define EPHSR_SQET_MASK 0x20 #define EPHSR_SQET_SHIFT 0x5 #define EPHSR_SQET_VAL(x) (((x) << EPHSR_SQET_SHIFT) & EPHSR_SQET_MASK) #define EPHSR_COL16_MASK 0x10 #define EPHSR_COL16_SHIFT 0x4 #define EPHSR_COL16_VAL(x) (((x) << EPHSR_COL16_SHIFT) & EPHSR_COL16_MASK) #define EPHSR_LTX_MULT_MASK 0x8 #define EPHSR_LTX_MULT_SHIFT 0x3 #define EPHSR_LTX_MULT_VAL(x) (((x) << EPHSR_LTX_MULT_SHIFT) & EPHSR_LTX_MULT_MASK) #define EPHSR_MUL_COL_MASK 0x4 #define EPHSR_MUL_COL_SHIFT 0x2 #define EPHSR_MUL_COL_VAL(x) (((x) << EPHSR_MUL_COL_SHIFT) & EPHSR_MUL_COL_MASK) #define EPHSR_SNGL_COL_MASK 0x2 #define EPHSR_SNGL_COL_SHIFT 0x1 #define EPHSR_SNGL_COL_VAL(x) (((x) << EPHSR_SNGL_COL_SHIFT) & EPHSR_SNGL_COL_MASK) #define EPHSR_TX_SUC_MASK 0x1 #define EPHSR_TX_SUC_SHIFT 0x0 #define EPHSR_TX_SUC_VAL(x) (((x) << EPHSR_TX_SUC_SHIFT) & EPHSR_TX_SUC_MASK) #define RCR_SOFT_RST_MASK 0x8000 #define RCR_SOFT_RST_SHIFT 0xF #define RCR_SOFT_RST_VAL(x) (((x) << RCR_SOFT_RST_SHIFT) & RCR_SOFT_RST_MASK) #define RCR_FILT_CAR_MASK 0x4000 #define RCR_FILT_CAR_SHIFT 0xE #define RCR_FILT_CAR_VAL(x) (((x) << RCR_FILT_CAR_SHIFT) & RCR_FILT_CAR_MASK) #define RCR_ABORT_ENB_MASK 0x2000 #define RCR_ABORT_ENB_SHIFT 0xD #define RCR_ABORT_ENB_VAL(x) (((x) << RCR_ABORT_ENB_SHIFT) & RCR_ABORT_ENB_MASK) #define RCR_RSV_12_12_MASK 0x1000 #define RCR_RSV_12_12_SHIFT 0xC #define RCR_RSV_12_12_VAL(x) (((x) << RCR_RSV_12_12_SHIFT) & RCR_RSV_12_12_MASK) #define RCR_RSV_11_11_MASK 0x800 #define RCR_RSV_11_11_SHIFT 0xB #define RCR_RSV_11_11_VAL(x) (((x) << RCR_RSV_11_11_SHIFT) & RCR_RSV_11_11_MASK) #define RCR_RSV_10_10_MASK 0x400 #define RCR_RSV_10_10_SHIFT 0xA #define RCR_RSV_10_10_VAL(x) (((x) << RCR_RSV_10_10_SHIFT) & RCR_RSV_10_10_MASK) #define RCR_STRIP_CRC_MASK 0x200 #define RCR_STRIP_CRC_SHIFT 0x9 #define RCR_STRIP_CRC_VAL(x) (((x) << RCR_STRIP_CRC_SHIFT) & RCR_STRIP_CRC_MASK) #define RCR_RXEN_MASK 0x100 #define RCR_RXEN_SHIFT 0x8 #define RCR_RXEN_VAL(x) (((x) << RCR_RXEN_SHIFT) & RCR_RXEN_MASK) #define RCR_RSV_7_7_MASK 0x80 #define RCR_RSV_7_7_SHIFT 0x7 #define RCR_RSV_7_7_VAL(x) (((x) << RCR_RSV_7_7_SHIFT) & RCR_RSV_7_7_MASK) #define RCR_RSV_6_6_MASK 0x40 #define RCR_RSV_6_6_SHIFT 0x6 #define RCR_RSV_6_6_VAL(x) (((x) << RCR_RSV_6_6_SHIFT) & RCR_RSV_6_6_MASK) #define RCR_RSV_5_5_MASK 0x20 #define RCR_RSV_5_5_SHIFT 0x5 #define RCR_RSV_5_5_VAL(x) (((x) << RCR_RSV_5_5_SHIFT) & RCR_RSV_5_5_MASK) #define RCR_RSV_4_4_MASK 0x10 #define RCR_RSV_4_4_SHIFT 0x4 #define RCR_RSV_4_4_VAL(x) (((x) << RCR_RSV_4_4_SHIFT) & RCR_RSV_4_4_MASK) #define RCR_RSV_3_3_MASK 0x8 #define RCR_RSV_3_3_SHIFT 0x3 #define RCR_RSV_3_3_VAL(x) (((x) << RCR_RSV_3_3_SHIFT) & RCR_RSV_3_3_MASK) #define RCR_ALMUL_MASK 0x4 #define RCR_ALMUL_SHIFT 0x2 #define RCR_ALMUL_VAL(x) (((x) << RCR_ALMUL_SHIFT) & RCR_ALMUL_MASK) #define RCR_PRMS_MASK 0x2 #define RCR_PRMS_SHIFT 0x1 #define RCR_PRMS_VAL(x) (((x) << RCR_PRMS_SHIFT) & RCR_PRMS_MASK) #define RCR_RX_ABORT_MASK 0x1 #define RCR_RX_ABORT_SHIFT 0x0 #define RCR_RX_ABORT_VAL(x) (((x) << RCR_RX_ABORT_SHIFT) & RCR_RX_ABORT_MASK) #define ECR_EXDTX_MASK 0xF000 #define ECR_EXDTX_SHIFT 0xC #define ECR_EXDTX_VAL(x) (((x) << ECR_EXDTX_SHIFT) & ECR_EXDTX_MASK) #define ECR_DTX_MASK 0xF00 #define ECR_DTX_SHIFT 0x8 #define ECR_DTX_VAL(x) (((x) << ECR_DTX_SHIFT) & ECR_DTX_MASK) #define ECR_MCOLN_MASK 0xF0 #define ECR_MCOLN_SHIFT 0x4 #define ECR_MCOLN_VAL(x) (((x) << ECR_MCOLN_SHIFT) & ECR_MCOLN_MASK) #define ECR_COLN_MASK 0xF #define ECR_COLN_SHIFT 0x0 #define ECR_COLN_VAL(x) (((x) << ECR_COLN_SHIFT) & ECR_COLN_MASK) #define MIR_AVAIL_MASK 0xFF00 #define MIR_AVAIL_SHIFT 0x8 #define MIR_AVAIL_VAL(x) (((x) << MIR_AVAIL_SHIFT) & MIR_AVAIL_MASK) #define MIR_SIZE_MASK 0xFF #define MIR_SIZE_SHIFT 0x0 #define MIR_SIZE_VAL(x) (((x) << MIR_SIZE_SHIFT) & MIR_SIZE_MASK) #define RPCR_RSV_15_15_MASK 0x8000 #define RPCR_RSV_15_15_SHIFT 0xF #define RPCR_RSV_15_15_VAL(x) (((x) << RPCR_RSV_15_15_SHIFT) & RPCR_RSV_15_15_MASK) #define RPCR_RSV_14_14_MASK 0x4000 #define RPCR_RSV_14_14_SHIFT 0xE #define RPCR_RSV_14_14_VAL(x) (((x) << RPCR_RSV_14_14_SHIFT) & RPCR_RSV_14_14_MASK) #define RPCR_SPEED_MASK 0x2000 #define RPCR_SPEED_SHIFT 0xD #define RPCR_SPEED_VAL(x) (((x) << RPCR_SPEED_SHIFT) & RPCR_SPEED_MASK) #define RPCR_DPLX_MASK 0x1000 #define RPCR_DPLX_SHIFT 0xC #define RPCR_DPLX_VAL(x) (((x) << RPCR_DPLX_SHIFT) & RPCR_DPLX_MASK) #define RPCR_ANEG_MASK 0x800 #define RPCR_ANEG_SHIFT 0xB #define RPCR_ANEG_VAL(x) (((x) << RPCR_ANEG_SHIFT) & RPCR_ANEG_MASK) #define RPCR_RSV_10_10_MASK 0x400 #define RPCR_RSV_10_10_SHIFT 0xA #define RPCR_RSV_10_10_VAL(x) (((x) << RPCR_RSV_10_10_SHIFT) & RPCR_RSV_10_10_MASK) #define RPCR_RSV_9_9_MASK 0x200 #define RPCR_RSV_9_9_SHIFT 0x9 #define RPCR_RSV_9_9_VAL(x) (((x) << RPCR_RSV_9_9_SHIFT) & RPCR_RSV_9_9_MASK) #define RPCR_RSV_8_8_MASK 0x100 #define RPCR_RSV_8_8_SHIFT 0x8 #define RPCR_RSV_8_8_VAL(x) (((x) << RPCR_RSV_8_8_SHIFT) & RPCR_RSV_8_8_MASK) #define RPCR_LEDA_MASK 0xE0 #define RPCR_LEDA_SHIFT 0x5 #define RPCR_LEDA_VAL(x) (((x) << RPCR_LEDA_SHIFT) & RPCR_LEDA_MASK) /* value options for bit RPCR_LEDA */ #define RPCR_LINK10or100 0 #define RPCR_LINK10 2 #define RPCR_FDX 3 #define RPCR_TXRX 4 #define RPCR_LINK100 5 #define RPCR_RX 6 #define RPCR_TX 7 #define RPCR_LEDB_MASK 0x1C #define RPCR_LEDB_SHIFT 0x2 #define RPCR_LEDB_VAL(x) (((x) << RPCR_LEDB_SHIFT) & RPCR_LEDB_MASK) /* value options for bit RPCR_LEDB */ #define RPCR_LINK10or100 0 #define RPCR_LINK10 2 #define RPCR_FDX 3 #define RPCR_TXRX 4 #define RPCR_LINK100 5 #define RPCR_RX 6 #define RPCR_TX 7 #define RPCR_RSV_1_1_MASK 0x2 #define RPCR_RSV_1_1_SHIFT 0x1 #define RPCR_RSV_1_1_VAL(x) (((x) << RPCR_RSV_1_1_SHIFT) & RPCR_RSV_1_1_MASK) #define RPCR_RSV_0_0_MASK 0x1 #define RPCR_RSV_0_0_SHIFT 0x0 #define RPCR_RSV_0_0_VAL(x) (((x) << RPCR_RSV_0_0_SHIFT) & RPCR_RSV_0_0_MASK) #define CR_EPH_Power_EN_MASK 0x8000 #define CR_EPH_Power_EN_SHIFT 0xF #define CR_EPH_Power_EN_VAL(x) (((x) << CR_EPH_Power_EN_SHIFT) & CR_EPH_Power_EN_MASK) #define CR_RSV_14_14_MASK 0x4000 #define CR_RSV_14_14_SHIFT 0xE #define CR_RSV_14_14_VAL(x) (((x) << CR_RSV_14_14_SHIFT) & CR_RSV_14_14_MASK) #define CR_RSV_13_13_MASK 0x2000 #define CR_RSV_13_13_SHIFT 0xD #define CR_RSV_13_13_VAL(x) (((x) << CR_RSV_13_13_SHIFT) & CR_RSV_13_13_MASK) #define CR_NO_WAIT_MASK 0x1000 #define CR_NO_WAIT_SHIFT 0xC #define CR_NO_WAIT_VAL(x) (((x) << CR_NO_WAIT_SHIFT) & CR_NO_WAIT_MASK) #define CR_RSV_11_11_MASK 0x800 #define CR_RSV_11_11_SHIFT 0xB #define CR_RSV_11_11_VAL(x) (((x) << CR_RSV_11_11_SHIFT) & CR_RSV_11_11_MASK) #define CR_GPCNTRL_MASK 0x400 #define CR_GPCNTRL_SHIFT 0xA #define CR_GPCNTRL_VAL(x) (((x) << CR_GPCNTRL_SHIFT) & CR_GPCNTRL_MASK) #define CR_EXT_PHY_MASK 0x200 #define CR_EXT_PHY_SHIFT 0x9 #define CR_EXT_PHY_VAL(x) (((x) << CR_EXT_PHY_SHIFT) & CR_EXT_PHY_MASK) #define CR_RSV_8_8_MASK 0x100 #define CR_RSV_8_8_SHIFT 0x8 #define CR_RSV_8_8_VAL(x) (((x) << CR_RSV_8_8_SHIFT) & CR_RSV_8_8_MASK) #define CR_RSV_7_7_MASK 0x80 #define CR_RSV_7_7_SHIFT 0x7 #define CR_RSV_7_7_VAL(x) (((x) << CR_RSV_7_7_SHIFT) & CR_RSV_7_7_MASK) #define CR_RSV_6_6_MASK 0x40 #define CR_RSV_6_6_SHIFT 0x6 #define CR_RSV_6_6_VAL(x) (((x) << CR_RSV_6_6_SHIFT) & CR_RSV_6_6_MASK) #define CR_RSV_3_5_MASK 0x38 #define CR_RSV_3_5_SHIFT 0x3 #define CR_RSV_3_5_VAL(x) (((x) << CR_RSV_3_5_SHIFT) & CR_RSV_3_5_MASK) #define CR_RSV_2_2_MASK 0x4 #define CR_RSV_2_2_SHIFT 0x2 #define CR_RSV_2_2_VAL(x) (((x) << CR_RSV_2_2_SHIFT) & CR_RSV_2_2_MASK) #define CR_RSV_1_1_MASK 0x2 #define CR_RSV_1_1_SHIFT 0x1 #define CR_RSV_1_1_VAL(x) (((x) << CR_RSV_1_1_SHIFT) & CR_RSV_1_1_MASK) #define CR_RSV_0_0_MASK 0x1 #define CR_RSV_0_0_SHIFT 0x0 #define CR_RSV_0_0_VAL(x) (((x) << CR_RSV_0_0_SHIFT) & CR_RSV_0_0_MASK) #define BAR_A15_13_MASK 0xE000 #define BAR_A15_13_SHIFT 0xD #define BAR_A15_13_VAL(x) (((x) << BAR_A15_13_SHIFT) & BAR_A15_13_MASK) #define BAR_A9_5_MASK 0x1F00 #define BAR_A9_5_SHIFT 0x8 #define BAR_A9_5_VAL(x) (((x) << BAR_A9_5_SHIFT) & BAR_A9_5_MASK) #define BAR_RSV_1_7_MASK 0xFE #define BAR_RSV_1_7_SHIFT 0x1 #define BAR_RSV_1_7_VAL(x) (((x) << BAR_RSV_1_7_SHIFT) & BAR_RSV_1_7_MASK) #define BAR_RSV_0_0_MASK 0x1 #define BAR_RSV_0_0_SHIFT 0x0 #define BAR_RSV_0_0_VAL(x) (((x) << BAR_RSV_0_0_SHIFT) & BAR_RSV_0_0_MASK) #define IAR1_0_A1_MASK 0xFF00 #define IAR1_0_A1_SHIFT 0x8 #define IAR1_0_A1_VAL(x) (((x) << IAR1_0_A1_SHIFT) & IAR1_0_A1_MASK) #define IAR1_0_A0_MASK 0xFF #define IAR1_0_A0_SHIFT 0x0 #define IAR1_0_A0_VAL(x) (((x) << IAR1_0_A0_SHIFT) & IAR1_0_A0_MASK) #define IAR3_2_A3_MASK 0xFF00 #define IAR3_2_A3_SHIFT 0x8 #define IAR3_2_A3_VAL(x) (((x) << IAR3_2_A3_SHIFT) & IAR3_2_A3_MASK) #define IAR3_2_A2_MASK 0xFF #define IAR3_2_A2_SHIFT 0x0 #define IAR3_2_A2_VAL(x) (((x) << IAR3_2_A2_SHIFT) & IAR3_2_A2_MASK) #define IAR5_4_A5_MASK 0xFF00 #define IAR5_4_A5_SHIFT 0x8 #define IAR5_4_A5_VAL(x) (((x) << IAR5_4_A5_SHIFT) & IAR5_4_A5_MASK) #define IAR5_4_A4_MASK 0xFF #define IAR5_4_A4_SHIFT 0x0 #define IAR5_4_A4_VAL(x) (((x) << IAR5_4_A4_SHIFT) & IAR5_4_A4_MASK) #define GPR_DATA_MASK 0xFFFF #define GPR_DATA_SHIFT 0x0 #define GPR_DATA_VAL(x) (((x) << GPR_DATA_SHIFT) & GPR_DATA_MASK) #define CTR_RSV_15_15_MASK 0x8000 #define CTR_RSV_15_15_SHIFT 0xF #define CTR_RSV_15_15_VAL(x) (((x) << CTR_RSV_15_15_SHIFT) & CTR_RSV_15_15_MASK) #define CTR_RCV_BAD_MASK 0x4000 #define CTR_RCV_BAD_SHIFT 0xE #define CTR_RCV_BAD_VAL(x) (((x) << CTR_RCV_BAD_SHIFT) & CTR_RCV_BAD_MASK) #define CTR_RSV_13_13_MASK 0x2000 #define CTR_RSV_13_13_SHIFT 0xD #define CTR_RSV_13_13_VAL(x) (((x) << CTR_RSV_13_13_SHIFT) & CTR_RSV_13_13_MASK) #define CTR_RSV_12_12_MASK 0x1000 #define CTR_RSV_12_12_SHIFT 0xC #define CTR_RSV_12_12_VAL(x) (((x) << CTR_RSV_12_12_SHIFT) & CTR_RSV_12_12_MASK) #define CTR_AUTO_RELEASE_MASK 0x800 #define CTR_AUTO_RELEASE_SHIFT 0xB #define CTR_AUTO_RELEASE_VAL(x) (((x) << CTR_AUTO_RELEASE_SHIFT) & CTR_AUTO_RELEASE_MASK) #define CTR_RSV_10_10_MASK 0x400 #define CTR_RSV_10_10_SHIFT 0xA #define CTR_RSV_10_10_VAL(x) (((x) << CTR_RSV_10_10_SHIFT) & CTR_RSV_10_10_MASK) #define CTR_RSV_9_9_MASK 0x200 #define CTR_RSV_9_9_SHIFT 0x9 #define CTR_RSV_9_9_VAL(x) (((x) << CTR_RSV_9_9_SHIFT) & CTR_RSV_9_9_MASK) #define CTR_RSV_8_8_MASK 0x100 #define CTR_RSV_8_8_SHIFT 0x8 #define CTR_RSV_8_8_VAL(x) (((x) << CTR_RSV_8_8_SHIFT) & CTR_RSV_8_8_MASK) #define CTR_LE_ENABLE_MASK 0x80 #define CTR_LE_ENABLE_SHIFT 0x7 #define CTR_LE_ENABLE_VAL(x) (((x) << CTR_LE_ENABLE_SHIFT) & CTR_LE_ENABLE_MASK) #define CTR_CR_ENABLE_MASK 0x40 #define CTR_CR_ENABLE_SHIFT 0x6 #define CTR_CR_ENABLE_VAL(x) (((x) << CTR_CR_ENABLE_SHIFT) & CTR_CR_ENABLE_MASK) #define CTR_TE_ENABLE_MASK 0x20 #define CTR_TE_ENABLE_SHIFT 0x5 #define CTR_TE_ENABLE_VAL(x) (((x) << CTR_TE_ENABLE_SHIFT) & CTR_TE_ENABLE_MASK) #define CTR_RSV_4_4_MASK 0x10 #define CTR_RSV_4_4_SHIFT 0x4 #define CTR_RSV_4_4_VAL(x) (((x) << CTR_RSV_4_4_SHIFT) & CTR_RSV_4_4_MASK) #define CTR_RSV_3_3_MASK 0x8 #define CTR_RSV_3_3_SHIFT 0x3 #define CTR_RSV_3_3_VAL(x) (((x) << CTR_RSV_3_3_SHIFT) & CTR_RSV_3_3_MASK) #define CTR_EEPROM_SELECT_MASK 0x4 #define CTR_EEPROM_SELECT_SHIFT 0x2 #define CTR_EEPROM_SELECT_VAL(x) (((x) << CTR_EEPROM_SELECT_SHIFT) & CTR_EEPROM_SELECT_MASK) #define CTR_RELOAD_MASK 0x2 #define CTR_RELOAD_SHIFT 0x1 #define CTR_RELOAD_VAL(x) (((x) << CTR_RELOAD_SHIFT) & CTR_RELOAD_MASK) #define CTR_STORE_MASK 0x1 #define CTR_STORE_SHIFT 0x0 #define CTR_STORE_VAL(x) (((x) << CTR_STORE_SHIFT) & CTR_STORE_MASK) #define MMUCR_RSV_15_15_MASK 0x8000 #define MMUCR_RSV_15_15_SHIFT 0xF #define MMUCR_RSV_15_15_VAL(x) (((x) << MMUCR_RSV_15_15_SHIFT) & MMUCR_RSV_15_15_MASK) #define MMUCR_RSV_14_14_MASK 0x4000 #define MMUCR_RSV_14_14_SHIFT 0xE #define MMUCR_RSV_14_14_VAL(x) (((x) << MMUCR_RSV_14_14_SHIFT) & MMUCR_RSV_14_14_MASK) #define MMUCR_RSV_13_13_MASK 0x2000 #define MMUCR_RSV_13_13_SHIFT 0xD #define MMUCR_RSV_13_13_VAL(x) (((x) << MMUCR_RSV_13_13_SHIFT) & MMUCR_RSV_13_13_MASK) #define MMUCR_RSV_12_12_MASK 0x1000 #define MMUCR_RSV_12_12_SHIFT 0xC #define MMUCR_RSV_12_12_VAL(x) (((x) << MMUCR_RSV_12_12_SHIFT) & MMUCR_RSV_12_12_MASK) #define MMUCR_RSV_11_11_MASK 0x800 #define MMUCR_RSV_11_11_SHIFT 0xB #define MMUCR_RSV_11_11_VAL(x) (((x) << MMUCR_RSV_11_11_SHIFT) & MMUCR_RSV_11_11_MASK) #define MMUCR_RSV_10_10_MASK 0x400 #define MMUCR_RSV_10_10_SHIFT 0xA #define MMUCR_RSV_10_10_VAL(x) (((x) << MMUCR_RSV_10_10_SHIFT) & MMUCR_RSV_10_10_MASK) #define MMUCR_RSV_9_9_MASK 0x200 #define MMUCR_RSV_9_9_SHIFT 0x9 #define MMUCR_RSV_9_9_VAL(x) (((x) << MMUCR_RSV_9_9_SHIFT) & MMUCR_RSV_9_9_MASK) #define MMUCR_RSV_8_8_MASK 0x100 #define MMUCR_RSV_8_8_SHIFT 0x8 #define MMUCR_RSV_8_8_VAL(x) (((x) << MMUCR_RSV_8_8_SHIFT) & MMUCR_RSV_8_8_MASK) #define MMUCR_CMD_MASK 0xE0 #define MMUCR_CMD_SHIFT 0x5 #define MMUCR_CMD_VAL(x) (((x) << MMUCR_CMD_SHIFT) & MMUCR_CMD_MASK) /* value options for bit MMUCR_CMD */ #define MMUCR_NOOP 0 #define MMUCR_TX_ALLOC 1 #define MMUCR_MMU_RESET 2 #define MMUCR_RX_FIFO_RM 3 #define MMUCR_RX_FIFO_RnR 4 #define MMUCR_RELEASE_PNO 5 #define MMUCR_ENQUEUE_PNO 6 #define MMUCR_RESET_TX_FIFOS 7 #define MMUCR_RSV_4_4_MASK 0x10 #define MMUCR_RSV_4_4_SHIFT 0x4 #define MMUCR_RSV_4_4_VAL(x) (((x) << MMUCR_RSV_4_4_SHIFT) & MMUCR_RSV_4_4_MASK) #define MMUCR_RSV_3_3_MASK 0x8 #define MMUCR_RSV_3_3_SHIFT 0x3 #define MMUCR_RSV_3_3_VAL(x) (((x) << MMUCR_RSV_3_3_SHIFT) & MMUCR_RSV_3_3_MASK) #define MMUCR_RSV_2_2_MASK 0x4 #define MMUCR_RSV_2_2_SHIFT 0x2 #define MMUCR_RSV_2_2_VAL(x) (((x) << MMUCR_RSV_2_2_SHIFT) & MMUCR_RSV_2_2_MASK) #define MMUCR_RSV_1_1_MASK 0x2 #define MMUCR_RSV_1_1_SHIFT 0x1 #define MMUCR_RSV_1_1_VAL(x) (((x) << MMUCR_RSV_1_1_SHIFT) & MMUCR_RSV_1_1_MASK) #define MMUCR_BUSY_MASK 0x1 #define MMUCR_BUSY_SHIFT 0x0 #define MMUCR_BUSY_VAL(x) (((x) << MMUCR_BUSY_SHIFT) & MMUCR_BUSY_MASK) #define PNR_RSV_8_15_MASK 0xFF00 #define PNR_RSV_8_15_SHIFT 0x8 #define PNR_RSV_8_15_VAL(x) (((x) << PNR_RSV_8_15_SHIFT) & PNR_RSV_8_15_MASK) #define PNR_RSV_7_7_MASK 0x80 #define PNR_RSV_7_7_SHIFT 0x7 #define PNR_RSV_7_7_VAL(x) (((x) << PNR_RSV_7_7_SHIFT) & PNR_RSV_7_7_MASK) #define PNR_RSV_6_6_MASK 0x40 #define PNR_RSV_6_6_SHIFT 0x6 #define PNR_RSV_6_6_VAL(x) (((x) << PNR_RSV_6_6_SHIFT) & PNR_RSV_6_6_MASK) #define PNR_PACKET_NUMBER_AT_TX_AREA_MASK 0x3F #define PNR_PACKET_NUMBER_AT_TX_AREA_SHIFT 0x0 #define PNR_PACKET_NUMBER_AT_TX_AREA_VAL(x) (((x) << PNR_PACKET_NUMBER_AT_TX_AREA_SHIFT) & PNR_PACKET_NUMBER_AT_TX_AREA_MASK) #define ARR_FAILED_MASK 0x8000 #define ARR_FAILED_SHIFT 0xF #define ARR_FAILED_VAL(x) (((x) << ARR_FAILED_SHIFT) & ARR_FAILED_MASK) #define ARR_RSV_14_14_MASK 0x4000 #define ARR_RSV_14_14_SHIFT 0xE #define ARR_RSV_14_14_VAL(x) (((x) << ARR_RSV_14_14_SHIFT) & ARR_RSV_14_14_MASK) #define ARR_ALLOCATED_PACKET_NUMBER_MASK 0x3F00 #define ARR_ALLOCATED_PACKET_NUMBER_SHIFT 0x8 #define ARR_ALLOCATED_PACKET_NUMBER_VAL(x) (((x) << ARR_ALLOCATED_PACKET_NUMBER_SHIFT) & ARR_ALLOCATED_PACKET_NUMBER_MASK) #define ARR_RSV_0_7_MASK 0xFF #define ARR_RSV_0_7_SHIFT 0x0 #define ARR_RSV_0_7_VAL(x) (((x) << ARR_RSV_0_7_SHIFT) & ARR_RSV_0_7_MASK) #define FIFO_REMPTY_MASK 0x8000 #define FIFO_REMPTY_SHIFT 0xF #define FIFO_REMPTY_VAL(x) (((x) << FIFO_REMPTY_SHIFT) & FIFO_REMPTY_MASK) #define FIFO_RSV_14_14_MASK 0x4000 #define FIFO_RSV_14_14_SHIFT 0xE #define FIFO_RSV_14_14_VAL(x) (((x) << FIFO_RSV_14_14_SHIFT) & FIFO_RSV_14_14_MASK) #define FIFO_RX_FIFO_PACKET_NUMBER_MASK 0x3F00 #define FIFO_RX_FIFO_PACKET_NUMBER_SHIFT 0x8 #define FIFO_RX_FIFO_PACKET_NUMBER_VAL(x) (((x) << FIFO_RX_FIFO_PACKET_NUMBER_SHIFT) & FIFO_RX_FIFO_PACKET_NUMBER_MASK) #define FIFO_TEMPTY_MASK 0x80 #define FIFO_TEMPTY_SHIFT 0x7 #define FIFO_TEMPTY_VAL(x) (((x) << FIFO_TEMPTY_SHIFT) & FIFO_TEMPTY_MASK) #define FIFO_RSV_6_6_MASK 0x40 #define FIFO_RSV_6_6_SHIFT 0x6 #define FIFO_RSV_6_6_VAL(x) (((x) << FIFO_RSV_6_6_SHIFT) & FIFO_RSV_6_6_MASK) #define FIFO_TX_FIFO_PACKET_NUMBER_MASK 0x3F #define FIFO_TX_FIFO_PACKET_NUMBER_SHIFT 0x0 #define FIFO_TX_FIFO_PACKET_NUMBER_VAL(x) (((x) << FIFO_TX_FIFO_PACKET_NUMBER_SHIFT) & FIFO_TX_FIFO_PACKET_NUMBER_MASK) #define PTR_RCV_MASK 0x8000 #define PTR_RCV_SHIFT 0xF #define PTR_RCV_VAL(x) (((x) << PTR_RCV_SHIFT) & PTR_RCV_MASK) #define PTR_AUTO_INCR_MASK 0x4000 #define PTR_AUTO_INCR_SHIFT 0xE #define PTR_AUTO_INCR_VAL(x) (((x) << PTR_AUTO_INCR_SHIFT) & PTR_AUTO_INCR_MASK) #define PTR_READ_MASK 0x2000 #define PTR_READ_SHIFT 0xD #define PTR_READ_VAL(x) (((x) << PTR_READ_SHIFT) & PTR_READ_MASK) #define PTR_ETEN_MASK 0x1000 #define PTR_ETEN_SHIFT 0xC #define PTR_ETEN_VAL(x) (((x) << PTR_ETEN_SHIFT) & PTR_ETEN_MASK) #define PTR_NOT_EMPTY_MASK 0x800 #define PTR_NOT_EMPTY_SHIFT 0xB #define PTR_NOT_EMPTY_VAL(x) (((x) << PTR_NOT_EMPTY_SHIFT) & PTR_NOT_EMPTY_MASK) #define PTR_POINTER_HIGH_MASK 0x700 #define PTR_POINTER_HIGH_SHIFT 0x8 #define PTR_POINTER_HIGH_VAL(x) (((x) << PTR_POINTER_HIGH_SHIFT) & PTR_POINTER_HIGH_MASK) #define PTR_POINTER_LOW_MASK 0xFF #define PTR_POINTER_LOW_SHIFT 0x0 #define PTR_POINTER_LOW_VAL(x) (((x) << PTR_POINTER_LOW_SHIFT) & PTR_POINTER_LOW_MASK) #define DATA_DATA_MASK 0xFFFF #define DATA_DATA_SHIFT 0x0 #define DATA_DATA_VAL(x) (((x) << DATA_DATA_SHIFT) & DATA_DATA_MASK) #define IST_RSV_8_15_MASK 0xFF00 #define IST_RSV_8_15_SHIFT 0x8 #define IST_RSV_8_15_VAL(x) (((x) << IST_RSV_8_15_SHIFT) & IST_RSV_8_15_MASK) #define IST_MDINT_MASK 0x80 #define IST_MDINT_SHIFT 0x7 #define IST_MDINT_VAL(x) (((x) << IST_MDINT_SHIFT) & IST_MDINT_MASK) #define IST_ERCV_INT_MASK 0x40 #define IST_ERCV_INT_SHIFT 0x6 #define IST_ERCV_INT_VAL(x) (((x) << IST_ERCV_INT_SHIFT) & IST_ERCV_INT_MASK) #define IST_EPH_INT_MASK 0x20 #define IST_EPH_INT_SHIFT 0x5 #define IST_EPH_INT_VAL(x) (((x) << IST_EPH_INT_SHIFT) & IST_EPH_INT_MASK) #define IST_RX_OVRN_INT_MASK 0x10 #define IST_RX_OVRN_INT_SHIFT 0x4 #define IST_RX_OVRN_INT_VAL(x) (((x) << IST_RX_OVRN_INT_SHIFT) & IST_RX_OVRN_INT_MASK) #define IST_ALLOC_INT_MASK 0x8 #define IST_ALLOC_INT_SHIFT 0x3 #define IST_ALLOC_INT_VAL(x) (((x) << IST_ALLOC_INT_SHIFT) & IST_ALLOC_INT_MASK) #define IST_TX_EMPTY_INT_MASK 0x4 #define IST_TX_EMPTY_INT_SHIFT 0x2 #define IST_TX_EMPTY_INT_VAL(x) (((x) << IST_TX_EMPTY_INT_SHIFT) & IST_TX_EMPTY_INT_MASK) #define IST_TX_INT_MASK 0x2 #define IST_TX_INT_SHIFT 0x1 #define IST_TX_INT_VAL(x) (((x) << IST_TX_INT_SHIFT) & IST_TX_INT_MASK) #define IST_RCV_INT_MASK 0x1 #define IST_RCV_INT_SHIFT 0x0 #define IST_RCV_INT_VAL(x) (((x) << IST_RCV_INT_SHIFT) & IST_RCV_INT_MASK) #define ACK_RSV_8_15_MASK 0xFF00 #define ACK_RSV_8_15_SHIFT 0x8 #define ACK_RSV_8_15_VAL(x) (((x) << ACK_RSV_8_15_SHIFT) & ACK_RSV_8_15_MASK) #define ACK_MDINT_MASK 0x80 #define ACK_MDINT_SHIFT 0x7 #define ACK_MDINT_VAL(x) (((x) << ACK_MDINT_SHIFT) & ACK_MDINT_MASK) #define ACK_ERCV_INT_MASK 0x40 #define ACK_ERCV_INT_SHIFT 0x6 #define ACK_ERCV_INT_VAL(x) (((x) << ACK_ERCV_INT_SHIFT) & ACK_ERCV_INT_MASK) #define ACK_RSV_5_5_MASK 0x20 #define ACK_RSV_5_5_SHIFT 0x5 #define ACK_RSV_5_5_VAL(x) (((x) << ACK_RSV_5_5_SHIFT) & ACK_RSV_5_5_MASK) #define ACK_RX_OVRN_INT_MASK 0x10 #define ACK_RX_OVRN_INT_SHIFT 0x4 #define ACK_RX_OVRN_INT_VAL(x) (((x) << ACK_RX_OVRN_INT_SHIFT) & ACK_RX_OVRN_INT_MASK) #define ACK_RSV_3_3_MASK 0x8 #define ACK_RSV_3_3_SHIFT 0x3 #define ACK_RSV_3_3_VAL(x) (((x) << ACK_RSV_3_3_SHIFT) & ACK_RSV_3_3_MASK) #define ACK_TX_EMPTY_INT_MASK 0x4 #define ACK_TX_EMPTY_INT_SHIFT 0x2 #define ACK_TX_EMPTY_INT_VAL(x) (((x) << ACK_TX_EMPTY_INT_SHIFT) & ACK_TX_EMPTY_INT_MASK) #define ACK_TX_INT_MASK 0x2 #define ACK_TX_INT_SHIFT 0x1 #define ACK_TX_INT_VAL(x) (((x) << ACK_TX_INT_SHIFT) & ACK_TX_INT_MASK) #define ACK_RSV_0_0_MASK 0x1 #define ACK_RSV_0_0_SHIFT 0x0 #define ACK_RSV_0_0_VAL(x) (((x) << ACK_RSV_0_0_SHIFT) & ACK_RSV_0_0_MASK) #define MSK_MDINT_MASK 0x8000 #define MSK_MDINT_SHIFT 0xF #define MSK_MDINT_VAL(x) (((x) << MSK_MDINT_SHIFT) & MSK_MDINT_MASK) #define MSK_ERCV_INT_MASK 0x4000 #define MSK_ERCV_INT_SHIFT 0xE #define MSK_ERCV_INT_VAL(x) (((x) << MSK_ERCV_INT_SHIFT) & MSK_ERCV_INT_MASK) #define MSK_EPH_INT_MASK 0x2000 #define MSK_EPH_INT_SHIFT 0xD #define MSK_EPH_INT_VAL(x) (((x) << MSK_EPH_INT_SHIFT) & MSK_EPH_INT_MASK) #define MSK_RX_OVRN_INT_MASK 0x1000 #define MSK_RX_OVRN_INT_SHIFT 0xC #define MSK_RX_OVRN_INT_VAL(x) (((x) << MSK_RX_OVRN_INT_SHIFT) & MSK_RX_OVRN_INT_MASK) #define MSK_ALLOC_INT_MASK 0x800 #define MSK_ALLOC_INT_SHIFT 0xB #define MSK_ALLOC_INT_VAL(x) (((x) << MSK_ALLOC_INT_SHIFT) & MSK_ALLOC_INT_MASK) #define MSK_TX_EMPTY_INT_MASK 0x400 #define MSK_TX_EMPTY_INT_SHIFT 0xA #define MSK_TX_EMPTY_INT_VAL(x) (((x) << MSK_TX_EMPTY_INT_SHIFT) & MSK_TX_EMPTY_INT_MASK) #define MSK_TX_INT_MASK 0x200 #define MSK_TX_INT_SHIFT 0x9 #define MSK_TX_INT_VAL(x) (((x) << MSK_TX_INT_SHIFT) & MSK_TX_INT_MASK) #define MSK_RCV_INT_MASK 0x100 #define MSK_RCV_INT_SHIFT 0x8 #define MSK_RCV_INT_VAL(x) (((x) << MSK_RCV_INT_SHIFT) & MSK_RCV_INT_MASK) #define MSK_RSV_0_7_MASK 0xFF #define MSK_RSV_0_7_SHIFT 0x0 #define MSK_RSV_0_7_VAL(x) (((x) << MSK_RSV_0_7_SHIFT) & MSK_RSV_0_7_MASK) #define MT1_0_MT1_MASK 0xFF00 #define MT1_0_MT1_SHIFT 0x8 #define MT1_0_MT1_VAL(x) (((x) << MT1_0_MT1_SHIFT) & MT1_0_MT1_MASK) #define MT1_0_MT0_MASK 0xFF #define MT1_0_MT0_SHIFT 0x0 #define MT1_0_MT0_VAL(x) (((x) << MT1_0_MT0_SHIFT) & MT1_0_MT0_MASK) #define MT3_2_MT3_MASK 0xFF00 #define MT3_2_MT3_SHIFT 0x8 #define MT3_2_MT3_VAL(x) (((x) << MT3_2_MT3_SHIFT) & MT3_2_MT3_MASK) #define MT3_2_MT2_MASK 0xFF #define MT3_2_MT2_SHIFT 0x0 #define MT3_2_MT2_VAL(x) (((x) << MT3_2_MT2_SHIFT) & MT3_2_MT2_MASK) #define MT5_4_MT5_MASK 0xFF00 #define MT5_4_MT5_SHIFT 0x8 #define MT5_4_MT5_VAL(x) (((x) << MT5_4_MT5_SHIFT) & MT5_4_MT5_MASK) #define MT5_4_MT4_MASK 0xFF #define MT5_4_MT4_SHIFT 0x0 #define MT5_4_MT4_VAL(x) (((x) << MT5_4_MT4_SHIFT) & MT5_4_MT4_MASK) #define MT7_6_MT7_MASK 0xFF00 #define MT7_6_MT7_SHIFT 0x8 #define MT7_6_MT7_VAL(x) (((x) << MT7_6_MT7_SHIFT) & MT7_6_MT7_MASK) #define MT7_6_MT6_MASK 0xFF #define MT7_6_MT6_SHIFT 0x0 #define MT7_6_MT6_VAL(x) (((x) << MT7_6_MT6_SHIFT) & MT7_6_MT6_MASK) #define MGMT_RSV_15_15_MASK 0x8000 #define MGMT_RSV_15_15_SHIFT 0xF #define MGMT_RSV_15_15_VAL(x) (((x) << MGMT_RSV_15_15_SHIFT) & MGMT_RSV_15_15_MASK) #define MGMT_MSK_CRS100_MASK 0x4000 #define MGMT_MSK_CRS100_SHIFT 0xE #define MGMT_MSK_CRS100_VAL(x) (((x) << MGMT_MSK_CRS100_SHIFT) & MGMT_MSK_CRS100_MASK) #define MGMT_RSV_13_13_MASK 0x2000 #define MGMT_RSV_13_13_SHIFT 0xD #define MGMT_RSV_13_13_VAL(x) (((x) << MGMT_RSV_13_13_SHIFT) & MGMT_RSV_13_13_MASK) #define MGMT_RSV_12_12_MASK 0x1000 #define MGMT_RSV_12_12_SHIFT 0xC #define MGMT_RSV_12_12_VAL(x) (((x) << MGMT_RSV_12_12_SHIFT) & MGMT_RSV_12_12_MASK) #define MGMT_RSV_11_11_MASK 0x800 #define MGMT_RSV_11_11_SHIFT 0xB #define MGMT_RSV_11_11_VAL(x) (((x) << MGMT_RSV_11_11_SHIFT) & MGMT_RSV_11_11_MASK) #define MGMT_RSV_10_10_MASK 0x400 #define MGMT_RSV_10_10_SHIFT 0xA #define MGMT_RSV_10_10_VAL(x) (((x) << MGMT_RSV_10_10_SHIFT) & MGMT_RSV_10_10_MASK) #define MGMT_RSV_9_9_MASK 0x200 #define MGMT_RSV_9_9_SHIFT 0x9 #define MGMT_RSV_9_9_VAL(x) (((x) << MGMT_RSV_9_9_SHIFT) & MGMT_RSV_9_9_MASK) #define MGMT_RSV_8_8_MASK 0x100 #define MGMT_RSV_8_8_SHIFT 0x8 #define MGMT_RSV_8_8_VAL(x) (((x) << MGMT_RSV_8_8_SHIFT) & MGMT_RSV_8_8_MASK) #define MGMT_RSV_4_7_MASK 0xF0 #define MGMT_RSV_4_7_SHIFT 0x4 #define MGMT_RSV_4_7_VAL(x) (((x) << MGMT_RSV_4_7_SHIFT) & MGMT_RSV_4_7_MASK) #define MGMT_MDOE_MASK 0x8 #define MGMT_MDOE_SHIFT 0x3 #define MGMT_MDOE_VAL(x) (((x) << MGMT_MDOE_SHIFT) & MGMT_MDOE_MASK) #define MGMT_MCLK_MASK 0x4 #define MGMT_MCLK_SHIFT 0x2 #define MGMT_MCLK_VAL(x) (((x) << MGMT_MCLK_SHIFT) & MGMT_MCLK_MASK) #define MGMT_MDIN_MASK 0x2 #define MGMT_MDIN_SHIFT 0x1 #define MGMT_MDIN_VAL(x) (((x) << MGMT_MDIN_SHIFT) & MGMT_MDIN_MASK) #define MGMT_MDOUT_MASK 0x1 #define MGMT_MDOUT_SHIFT 0x0 #define MGMT_MDOUT_VAL(x) (((x) << MGMT_MDOUT_SHIFT) & MGMT_MDOUT_MASK) #define REV_RSV_8_15_MASK 0xFF00 #define REV_RSV_8_15_SHIFT 0x8 #define REV_RSV_8_15_VAL(x) (((x) << REV_RSV_8_15_SHIFT) & REV_RSV_8_15_MASK) #define REV_CHIP_MASK 0xF0 #define REV_CHIP_SHIFT 0x4 #define REV_CHIP_VAL(x) (((x) << REV_CHIP_SHIFT) & REV_CHIP_MASK) #define REV_REV_MASK 0xF #define REV_REV_SHIFT 0x0 #define REV_REV_VAL(x) (((x) << REV_REV_SHIFT) & REV_REV_MASK) #define ERCV_RSV_8_15_MASK 0xFF00 #define ERCV_RSV_8_15_SHIFT 0x8 #define ERCV_RSV_8_15_VAL(x) (((x) << ERCV_RSV_8_15_SHIFT) & ERCV_RSV_8_15_MASK) #define ERCV_RCV_DISCRD_MASK 0x80 #define ERCV_RCV_DISCRD_SHIFT 0x7 #define ERCV_RCV_DISCRD_VAL(x) (((x) << ERCV_RCV_DISCRD_SHIFT) & ERCV_RCV_DISCRD_MASK) #define ERCV_RSV_6_6_MASK 0x40 #define ERCV_RSV_6_6_SHIFT 0x6 #define ERCV_RSV_6_6_VAL(x) (((x) << ERCV_RSV_6_6_SHIFT) & ERCV_RSV_6_6_MASK) #define ERCV_RSV_5_5_MASK 0x20 #define ERCV_RSV_5_5_SHIFT 0x5 #define ERCV_RSV_5_5_VAL(x) (((x) << ERCV_RSV_5_5_SHIFT) & ERCV_RSV_5_5_MASK) #define ERCV_ERCV_THRESHOLD_MASK 0x1F #define ERCV_ERCV_THRESHOLD_SHIFT 0x0 #define ERCV_ERCV_THRESHOLD_VAL(x) (((x) << ERCV_ERCV_THRESHOLD_SHIFT) & ERCV_ERCV_THRESHOLD_MASK) #define Control_RST_MASK 0x8000 #define Control_RST_SHIFT 0xF #define Control_RST_VAL(x) (((x) << Control_RST_SHIFT) & Control_RST_MASK) #define Control_LPBK_MASK 0x4000 #define Control_LPBK_SHIFT 0xE #define Control_LPBK_VAL(x) (((x) << Control_LPBK_SHIFT) & Control_LPBK_MASK) #define Control_SPEED_MASK 0x2000 #define Control_SPEED_SHIFT 0xD #define Control_SPEED_VAL(x) (((x) << Control_SPEED_SHIFT) & Control_SPEED_MASK) #define Control_ANEG_EN_MASK 0x1000 #define Control_ANEG_EN_SHIFT 0xC #define Control_ANEG_EN_VAL(x) (((x) << Control_ANEG_EN_SHIFT) & Control_ANEG_EN_MASK) #define Control_PDN_MASK 0x800 #define Control_PDN_SHIFT 0xB #define Control_PDN_VAL(x) (((x) << Control_PDN_SHIFT) & Control_PDN_MASK) #define Control_MII_DIS_MASK 0x400 #define Control_MII_DIS_SHIFT 0xA #define Control_MII_DIS_VAL(x) (((x) << Control_MII_DIS_SHIFT) & Control_MII_DIS_MASK) #define Control_ANEG_RST_MASK 0x200 #define Control_ANEG_RST_SHIFT 0x9 #define Control_ANEG_RST_VAL(x) (((x) << Control_ANEG_RST_SHIFT) & Control_ANEG_RST_MASK) #define Control_DPLX_MASK 0x100 #define Control_DPLX_SHIFT 0x8 #define Control_DPLX_VAL(x) (((x) << Control_DPLX_SHIFT) & Control_DPLX_MASK) #define Control_COLST_MASK 0x80 #define Control_COLST_SHIFT 0x7 #define Control_COLST_VAL(x) (((x) << Control_COLST_SHIFT) & Control_COLST_MASK) #define Control_RSV_0_6_MASK 0x7F #define Control_RSV_0_6_SHIFT 0x0 #define Control_RSV_0_6_VAL(x) (((x) << Control_RSV_0_6_SHIFT) & Control_RSV_0_6_MASK) #define Status_CAP_T4_MASK 0x8000 #define Status_CAP_T4_SHIFT 0xF #define Status_CAP_T4_VAL(x) (((x) << Status_CAP_T4_SHIFT) & Status_CAP_T4_MASK) #define Status_CAP_TXF_MASK 0x4000 #define Status_CAP_TXF_SHIFT 0xE #define Status_CAP_TXF_VAL(x) (((x) << Status_CAP_TXF_SHIFT) & Status_CAP_TXF_MASK) #define Status_CAP_TXH_MASK 0x2000 #define Status_CAP_TXH_SHIFT 0xD #define Status_CAP_TXH_VAL(x) (((x) << Status_CAP_TXH_SHIFT) & Status_CAP_TXH_MASK) #define Status_CAP_TF_MASK 0x1000 #define Status_CAP_TF_SHIFT 0xC #define Status_CAP_TF_VAL(x) (((x) << Status_CAP_TF_SHIFT) & Status_CAP_TF_MASK) #define Status_CAP_TH_MASK 0x800 #define Status_CAP_TH_SHIFT 0xB #define Status_CAP_TH_VAL(x) (((x) << Status_CAP_TH_SHIFT) & Status_CAP_TH_MASK) #define Status_RSV_7_10_MASK 0x780 #define Status_RSV_7_10_SHIFT 0x7 #define Status_RSV_7_10_VAL(x) (((x) << Status_RSV_7_10_SHIFT) & Status_RSV_7_10_MASK) #define Status_CAP_SUPR_MASK 0x40 #define Status_CAP_SUPR_SHIFT 0x6 #define Status_CAP_SUPR_VAL(x) (((x) << Status_CAP_SUPR_SHIFT) & Status_CAP_SUPR_MASK) #define Status_ANEG_ACK_MASK 0x20 #define Status_ANEG_ACK_SHIFT 0x5 #define Status_ANEG_ACK_VAL(x) (((x) << Status_ANEG_ACK_SHIFT) & Status_ANEG_ACK_MASK) #define Status_REM_FLT_MASK 0x10 #define Status_REM_FLT_SHIFT 0x4 #define Status_REM_FLT_VAL(x) (((x) << Status_REM_FLT_SHIFT) & Status_REM_FLT_MASK) #define Status_CAP_ANEG_MASK 0x8 #define Status_CAP_ANEG_SHIFT 0x3 #define Status_CAP_ANEG_VAL(x) (((x) << Status_CAP_ANEG_SHIFT) & Status_CAP_ANEG_MASK) #define Status_LINK_MASK 0x4 #define Status_LINK_SHIFT 0x2 #define Status_LINK_VAL(x) (((x) << Status_LINK_SHIFT) & Status_LINK_MASK) #define Status_JAB_MASK 0x2 #define Status_JAB_SHIFT 0x1 #define Status_JAB_VAL(x) (((x) << Status_JAB_SHIFT) & Status_JAB_MASK) #define Status_EXREG_MASK 0x1 #define Status_EXREG_SHIFT 0x0 #define Status_EXREG_VAL(x) (((x) << Status_EXREG_SHIFT) & Status_EXREG_MASK) #define PHY_ID1_VENDOR_MASK 0xFFFF #define PHY_ID1_VENDOR_SHIFT 0x0 #define PHY_ID1_VENDOR_VAL(x) (((x) << PHY_ID1_VENDOR_SHIFT) & PHY_ID1_VENDOR_MASK) #define PHY_ID2_OUILSB_MASK 0xFC00 #define PHY_ID2_OUILSB_SHIFT 0xA #define PHY_ID2_OUILSB_VAL(x) (((x) << PHY_ID2_OUILSB_SHIFT) & PHY_ID2_OUILSB_MASK) #define PHY_ID2_MFGR_MASK 0x3F0 #define PHY_ID2_MFGR_SHIFT 0x4 #define PHY_ID2_MFGR_VAL(x) (((x) << PHY_ID2_MFGR_SHIFT) & PHY_ID2_MFGR_MASK) #define PHY_ID2_REV_MASK 0xF #define PHY_ID2_REV_SHIFT 0x0 #define PHY_ID2_REV_VAL(x) (((x) << PHY_ID2_REV_SHIFT) & PHY_ID2_REV_MASK) #define ANA_NP_MASK 0x8000 #define ANA_NP_SHIFT 0xF #define ANA_NP_VAL(x) (((x) << ANA_NP_SHIFT) & ANA_NP_MASK) #define ANA_ACK_MASK 0x4000 #define ANA_ACK_SHIFT 0xE #define ANA_ACK_VAL(x) (((x) << ANA_ACK_SHIFT) & ANA_ACK_MASK) #define ANA_RF_MASK 0x2000 #define ANA_RF_SHIFT 0xD #define ANA_RF_VAL(x) (((x) << ANA_RF_SHIFT) & ANA_RF_MASK) #define ANA_RSV_10_12_MASK 0x1C00 #define ANA_RSV_10_12_SHIFT 0xA #define ANA_RSV_10_12_VAL(x) (((x) << ANA_RSV_10_12_SHIFT) & ANA_RSV_10_12_MASK) #define ANA_T4_MASK 0x200 #define ANA_T4_SHIFT 0x9 #define ANA_T4_VAL(x) (((x) << ANA_T4_SHIFT) & ANA_T4_MASK) #define ANA_TX_FDX_MASK 0x100 #define ANA_TX_FDX_SHIFT 0x8 #define ANA_TX_FDX_VAL(x) (((x) << ANA_TX_FDX_SHIFT) & ANA_TX_FDX_MASK) #define ANA_TX_HDX_MASK 0x80 #define ANA_TX_HDX_SHIFT 0x7 #define ANA_TX_HDX_VAL(x) (((x) << ANA_TX_HDX_SHIFT) & ANA_TX_HDX_MASK) #define ANA_TEN_FDX_MASK 0x40 #define ANA_TEN_FDX_SHIFT 0x6 #define ANA_TEN_FDX_VAL(x) (((x) << ANA_TEN_FDX_SHIFT) & ANA_TEN_FDX_MASK) #define ANA_TEN_HDX_MASK 0x20 #define ANA_TEN_HDX_SHIFT 0x5 #define ANA_TEN_HDX_VAL(x) (((x) << ANA_TEN_HDX_SHIFT) & ANA_TEN_HDX_MASK) #define ANA_RSV_1_4_MASK 0x1E #define ANA_RSV_1_4_SHIFT 0x1 #define ANA_RSV_1_4_VAL(x) (((x) << ANA_RSV_1_4_SHIFT) & ANA_RSV_1_4_MASK) #define ANA_CSMA_MASK 0x1 #define ANA_CSMA_SHIFT 0x0 #define ANA_CSMA_VAL(x) (((x) << ANA_CSMA_SHIFT) & ANA_CSMA_MASK) #define ANREC_NP_MASK 0x8000 #define ANREC_NP_SHIFT 0xF #define ANREC_NP_VAL(x) (((x) << ANREC_NP_SHIFT) & ANREC_NP_MASK) #define ANREC_ACK_MASK 0x4000 #define ANREC_ACK_SHIFT 0xE #define ANREC_ACK_VAL(x) (((x) << ANREC_ACK_SHIFT) & ANREC_ACK_MASK) #define ANREC_RF_MASK 0x2000 #define ANREC_RF_SHIFT 0xD #define ANREC_RF_VAL(x) (((x) << ANREC_RF_SHIFT) & ANREC_RF_MASK) #define ANREC_RSV_10_12_MASK 0x1C00 #define ANREC_RSV_10_12_SHIFT 0xA #define ANREC_RSV_10_12_VAL(x) (((x) << ANREC_RSV_10_12_SHIFT) & ANREC_RSV_10_12_MASK) #define ANREC_T4_MASK 0x200 #define ANREC_T4_SHIFT 0x9 #define ANREC_T4_VAL(x) (((x) << ANREC_T4_SHIFT) & ANREC_T4_MASK) #define ANREC_TX_FDX_MASK 0x100 #define ANREC_TX_FDX_SHIFT 0x8 #define ANREC_TX_FDX_VAL(x) (((x) << ANREC_TX_FDX_SHIFT) & ANREC_TX_FDX_MASK) #define ANREC_TX_HDX_MASK 0x80 #define ANREC_TX_HDX_SHIFT 0x7 #define ANREC_TX_HDX_VAL(x) (((x) << ANREC_TX_HDX_SHIFT) & ANREC_TX_HDX_MASK) #define ANREC_TEN_FDX_MASK 0x40 #define ANREC_TEN_FDX_SHIFT 0x6 #define ANREC_TEN_FDX_VAL(x) (((x) << ANREC_TEN_FDX_SHIFT) & ANREC_TEN_FDX_MASK) #define ANREC_TEN_HDX_MASK 0x20 #define ANREC_TEN_HDX_SHIFT 0x5 #define ANREC_TEN_HDX_VAL(x) (((x) << ANREC_TEN_HDX_SHIFT) & ANREC_TEN_HDX_MASK) #define ANREC_RSV_1_4_MASK 0x1E #define ANREC_RSV_1_4_SHIFT 0x1 #define ANREC_RSV_1_4_VAL(x) (((x) << ANREC_RSV_1_4_SHIFT) & ANREC_RSV_1_4_MASK) #define ANREC_CSMA_MASK 0x1 #define ANREC_CSMA_SHIFT 0x0 #define ANREC_CSMA_VAL(x) (((x) << ANREC_CSMA_SHIFT) & ANREC_CSMA_MASK) #define Config1_LNKDIS_MASK 0x8000 #define Config1_LNKDIS_SHIFT 0xF #define Config1_LNKDIS_VAL(x) (((x) << Config1_LNKDIS_SHIFT) & Config1_LNKDIS_MASK) #define Config1_XMTDIS_MASK 0x4000 #define Config1_XMTDIS_SHIFT 0xE #define Config1_XMTDIS_VAL(x) (((x) << Config1_XMTDIS_SHIFT) & Config1_XMTDIS_MASK) #define Config1_XMTPDN_MASK 0x2000 #define Config1_XMTPDN_SHIFT 0xD #define Config1_XMTPDN_VAL(x) (((x) << Config1_XMTPDN_SHIFT) & Config1_XMTPDN_MASK) #define Config1_RSV_11_12_MASK 0x1800 #define Config1_RSV_11_12_SHIFT 0xB #define Config1_RSV_11_12_VAL(x) (((x) << Config1_RSV_11_12_SHIFT) & Config1_RSV_11_12_MASK) #define Config1_BYPSCR_MASK 0x400 #define Config1_BYPSCR_SHIFT 0xA #define Config1_BYPSCR_VAL(x) (((x) << Config1_BYPSCR_SHIFT) & Config1_BYPSCR_MASK) #define Config1_UNSCDS_MASK 0x200 #define Config1_UNSCDS_SHIFT 0x9 #define Config1_UNSCDS_VAL(x) (((x) << Config1_UNSCDS_SHIFT) & Config1_UNSCDS_MASK) #define Config1_EQLZR_MASK 0x100 #define Config1_EQLZR_SHIFT 0x8 #define Config1_EQLZR_VAL(x) (((x) << Config1_EQLZR_SHIFT) & Config1_EQLZR_MASK) #define Config1_CABLE_MASK 0x80 #define Config1_CABLE_SHIFT 0x7 #define Config1_CABLE_VAL(x) (((x) << Config1_CABLE_SHIFT) & Config1_CABLE_MASK) #define Config1_RLVL_MASK 0x40 #define Config1_RLVL_SHIFT 0x6 #define Config1_RLVL_VAL(x) (((x) << Config1_RLVL_SHIFT) & Config1_RLVL_MASK) #define Config1_TLVL_MASK 0x3C #define Config1_TLVL_SHIFT 0x2 #define Config1_TLVL_VAL(x) (((x) << Config1_TLVL_SHIFT) & Config1_TLVL_MASK) #define Config1_TRF_MASK 0x3 #define Config1_TRF_SHIFT 0x0 #define Config1_TRF_VAL(x) (((x) << Config1_TRF_SHIFT) & Config1_TRF_MASK) #define Config2_RSV_6_15_MASK 0xFFC0 #define Config2_RSV_6_15_SHIFT 0x6 #define Config2_RSV_6_15_VAL(x) (((x) << Config2_RSV_6_15_SHIFT) & Config2_RSV_6_15_MASK) #define Config2_APOLDIS_MASK 0x20 #define Config2_APOLDIS_SHIFT 0x5 #define Config2_APOLDIS_VAL(x) (((x) << Config2_APOLDIS_SHIFT) & Config2_APOLDIS_MASK) #define Config2_JABDIS_MASK 0x10 #define Config2_JABDIS_SHIFT 0x4 #define Config2_JABDIS_VAL(x) (((x) << Config2_JABDIS_SHIFT) & Config2_JABDIS_MASK) #define Config2_MREG_MASK 0x8 #define Config2_MREG_SHIFT 0x3 #define Config2_MREG_VAL(x) (((x) << Config2_MREG_SHIFT) & Config2_MREG_MASK) #define Config2_INTMDIO_MASK 0x4 #define Config2_INTMDIO_SHIFT 0x2 #define Config2_INTMDIO_VAL(x) (((x) << Config2_INTMDIO_SHIFT) & Config2_INTMDIO_MASK) #define Config2_RSV_0_1_MASK 0x3 #define Config2_RSV_0_1_SHIFT 0x0 #define Config2_RSV_0_1_VAL(x) (((x) << Config2_RSV_0_1_SHIFT) & Config2_RSV_0_1_MASK) #define Status_Output_INT_MASK 0x8000 #define Status_Output_INT_SHIFT 0xF #define Status_Output_INT_VAL(x) (((x) << Status_Output_INT_SHIFT) & Status_Output_INT_MASK) #define Status_Output_LNKFAIL_MASK 0x4000 #define Status_Output_LNKFAIL_SHIFT 0xE #define Status_Output_LNKFAIL_VAL(x) (((x) << Status_Output_LNKFAIL_SHIFT) & Status_Output_LNKFAIL_MASK) #define Status_Output_LOSSSYNC_MASK 0x2000 #define Status_Output_LOSSSYNC_SHIFT 0xD #define Status_Output_LOSSSYNC_VAL(x) (((x) << Status_Output_LOSSSYNC_SHIFT) & Status_Output_LOSSSYNC_MASK) #define Status_Output_CWRD_MASK 0x1000 #define Status_Output_CWRD_SHIFT 0xC #define Status_Output_CWRD_VAL(x) (((x) << Status_Output_CWRD_SHIFT) & Status_Output_CWRD_MASK) #define Status_Output_SSD_MASK 0x800 #define Status_Output_SSD_SHIFT 0xB #define Status_Output_SSD_VAL(x) (((x) << Status_Output_SSD_SHIFT) & Status_Output_SSD_MASK) #define Status_Output_ESD_MASK 0x400 #define Status_Output_ESD_SHIFT 0xA #define Status_Output_ESD_VAL(x) (((x) << Status_Output_ESD_SHIFT) & Status_Output_ESD_MASK) #define Status_Output_RPOL_MASK 0x200 #define Status_Output_RPOL_SHIFT 0x9 #define Status_Output_RPOL_VAL(x) (((x) << Status_Output_RPOL_SHIFT) & Status_Output_RPOL_MASK) #define Status_Output_JAB_MASK 0x100 #define Status_Output_JAB_SHIFT 0x8 #define Status_Output_JAB_VAL(x) (((x) << Status_Output_JAB_SHIFT) & Status_Output_JAB_MASK) #define Status_Output_SPDDET_MASK 0x80 #define Status_Output_SPDDET_SHIFT 0x7 #define Status_Output_SPDDET_VAL(x) (((x) << Status_Output_SPDDET_SHIFT) & Status_Output_SPDDET_MASK) #define Status_Output_DPLXDET_MASK 0x40 #define Status_Output_DPLXDET_SHIFT 0x6 #define Status_Output_DPLXDET_VAL(x) (((x) << Status_Output_DPLXDET_SHIFT) & Status_Output_DPLXDET_MASK) #define Status_Output_RSV_0_5_MASK 0x3F #define Status_Output_RSV_0_5_SHIFT 0x0 #define Status_Output_RSV_0_5_VAL(x) (((x) << Status_Output_RSV_0_5_SHIFT) & Status_Output_RSV_0_5_MASK) #define Mask_MINT_MASK 0x8000 #define Mask_MINT_SHIFT 0xF #define Mask_MINT_VAL(x) (((x) << Mask_MINT_SHIFT) & Mask_MINT_MASK) #define Mask_MLNKFAIL_MASK 0x4000 #define Mask_MLNKFAIL_SHIFT 0xE #define Mask_MLNKFAIL_VAL(x) (((x) << Mask_MLNKFAIL_SHIFT) & Mask_MLNKFAIL_MASK) #define Mask_MLOSSSYN_MASK 0x2000 #define Mask_MLOSSSYN_SHIFT 0xD #define Mask_MLOSSSYN_VAL(x) (((x) << Mask_MLOSSSYN_SHIFT) & Mask_MLOSSSYN_MASK) #define Mask_MCWRD_MASK 0x1000 #define Mask_MCWRD_SHIFT 0xC #define Mask_MCWRD_VAL(x) (((x) << Mask_MCWRD_SHIFT) & Mask_MCWRD_MASK) #define Mask_MSSD_MASK 0x800 #define Mask_MSSD_SHIFT 0xB #define Mask_MSSD_VAL(x) (((x) << Mask_MSSD_SHIFT) & Mask_MSSD_MASK) #define Mask_MESD_MASK 0x400 #define Mask_MESD_SHIFT 0xA #define Mask_MESD_VAL(x) (((x) << Mask_MESD_SHIFT) & Mask_MESD_MASK) #define Mask_MRPOL_MASK 0x200 #define Mask_MRPOL_SHIFT 0x9 #define Mask_MRPOL_VAL(x) (((x) << Mask_MRPOL_SHIFT) & Mask_MRPOL_MASK) #define Mask_MJAB_MASK 0x100 #define Mask_MJAB_SHIFT 0x8 #define Mask_MJAB_VAL(x) (((x) << Mask_MJAB_SHIFT) & Mask_MJAB_MASK) #define Mask_MSPDDT_MASK 0x80 #define Mask_MSPDDT_SHIFT 0x7 #define Mask_MSPDDT_VAL(x) (((x) << Mask_MSPDDT_SHIFT) & Mask_MSPDDT_MASK) #define Mask_MDPLDT_MASK 0x40 #define Mask_MDPLDT_SHIFT 0x6 #define Mask_MDPLDT_VAL(x) (((x) << Mask_MDPLDT_SHIFT) & Mask_MDPLDT_MASK) #define Mask_RSV_0_5_MASK 0x3F #define Mask_RSV_0_5_SHIFT 0x0 #define Mask_RSV_0_5_VAL(x) (((x) << Mask_RSV_0_5_SHIFT) & Mask_RSV_0_5_MASK) #define Reserved_RSV_0_15_MASK 0xFFFF #define Reserved_RSV_0_15_SHIFT 0x0 #define Reserved_RSV_0_15_VAL(x) (((x) << Reserved_RSV_0_15_SHIFT) & Reserved_RSV_0_15_MASK) static inline u_int16_t get_BSR(void); static inline void set_BSR(u_int16_t val); static inline u_int8_t get_BSR_ID(void); static inline void set_BSR_ID(u_int8_t bit_val); static inline u_int8_t mem_get_BSR_ID(u_int16_t reg_val); static inline void mem_set_BSR_ID(u_int16_t *reg_val, u_int8_t bit_val); /* Warning: dont_change and volatile for register BSR bit BANK */ static inline u_int8_t get_BSR_BANK(void); static inline void set_BSR_BANK(u_int8_t bit_val); static inline u_int8_t mem_get_BSR_BANK(u_int16_t reg_val); static inline void mem_set_BSR_BANK(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_TCR(void); static inline void set_TCR(u_int16_t val); static inline u_int8_t get_TCR_SWFDUP(void); static inline void set_TCR_SWFDUP(u_int8_t bit_val); static inline u_int8_t mem_get_TCR_SWFDUP(u_int16_t reg_val); static inline void mem_set_TCR_SWFDUP(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_TCR_EPH_LOOP(void); static inline void set_TCR_EPH_LOOP(u_int8_t bit_val); static inline u_int8_t mem_get_TCR_EPH_LOOP(u_int16_t reg_val); static inline void mem_set_TCR_EPH_LOOP(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_TCR_STP_SQET(void); static inline void set_TCR_STP_SQET(u_int8_t bit_val); static inline u_int8_t mem_get_TCR_STP_SQET(u_int16_t reg_val); static inline void mem_set_TCR_STP_SQET(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_TCR_FDUPLX(void); static inline void set_TCR_FDUPLX(u_int8_t bit_val); static inline u_int8_t mem_get_TCR_FDUPLX(u_int16_t reg_val); static inline void mem_set_TCR_FDUPLX(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_TCR_MON_CSN(void); static inline void set_TCR_MON_CSN(u_int8_t bit_val); static inline u_int8_t mem_get_TCR_MON_CSN(u_int16_t reg_val); static inline void mem_set_TCR_MON_CSN(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_TCR_NOCRC(void); static inline void set_TCR_NOCRC(u_int8_t bit_val); static inline u_int8_t mem_get_TCR_NOCRC(u_int16_t reg_val); static inline void mem_set_TCR_NOCRC(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_TCR_PAD_EN(void); static inline void set_TCR_PAD_EN(u_int8_t bit_val); static inline u_int8_t mem_get_TCR_PAD_EN(u_int16_t reg_val); static inline void mem_set_TCR_PAD_EN(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_TCR_FORCOL(void); static inline void set_TCR_FORCOL(u_int8_t bit_val); static inline u_int8_t mem_get_TCR_FORCOL(u_int16_t reg_val); static inline void mem_set_TCR_FORCOL(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_TCR_LOOP(void); static inline void set_TCR_LOOP(u_int8_t bit_val); static inline u_int8_t mem_get_TCR_LOOP(u_int16_t reg_val); static inline void mem_set_TCR_LOOP(u_int16_t *reg_val, u_int8_t bit_val); /* Warning: dont_change and volatile for register TCR bit TXENA */ static inline u_int8_t get_TCR_TXENA(void); static inline void set_TCR_TXENA(u_int8_t bit_val); static inline u_int8_t mem_get_TCR_TXENA(u_int16_t reg_val); static inline void mem_set_TCR_TXENA(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_EPHSR(void); static inline u_int8_t get_EPHSR_TX_UNRN(void); static inline u_int8_t mem_get_EPHSR_TX_UNRN(u_int16_t reg_val); static inline void mem_set_EPHSR_TX_UNRN(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_EPHSR_LINK_OK(void); static inline u_int8_t mem_get_EPHSR_LINK_OK(u_int16_t reg_val); static inline void mem_set_EPHSR_LINK_OK(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_EPHSR_CTR_ROL(void); static inline u_int8_t mem_get_EPHSR_CTR_ROL(u_int16_t reg_val); static inline void mem_set_EPHSR_CTR_ROL(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_EPHSR_EXC_DEF(void); static inline u_int8_t mem_get_EPHSR_EXC_DEF(u_int16_t reg_val); static inline void mem_set_EPHSR_EXC_DEF(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_EPHSR_LOST_CAR(void); static inline u_int8_t mem_get_EPHSR_LOST_CAR(u_int16_t reg_val); static inline void mem_set_EPHSR_LOST_CAR(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_EPHSR_LATCOL(void); static inline u_int8_t mem_get_EPHSR_LATCOL(u_int16_t reg_val); static inline void mem_set_EPHSR_LATCOL(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_EPHSR_TX_DEFR(void); static inline u_int8_t mem_get_EPHSR_TX_DEFR(u_int16_t reg_val); static inline void mem_set_EPHSR_TX_DEFR(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_EPHSR_LTX_BRD(void); static inline u_int8_t mem_get_EPHSR_LTX_BRD(u_int16_t reg_val); static inline void mem_set_EPHSR_LTX_BRD(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_EPHSR_SQET(void); static inline u_int8_t mem_get_EPHSR_SQET(u_int16_t reg_val); static inline void mem_set_EPHSR_SQET(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_EPHSR_COL16(void); static inline u_int8_t mem_get_EPHSR_COL16(u_int16_t reg_val); static inline void mem_set_EPHSR_COL16(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_EPHSR_LTX_MULT(void); static inline u_int8_t mem_get_EPHSR_LTX_MULT(u_int16_t reg_val); static inline void mem_set_EPHSR_LTX_MULT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_EPHSR_MUL_COL(void); static inline u_int8_t mem_get_EPHSR_MUL_COL(u_int16_t reg_val); static inline void mem_set_EPHSR_MUL_COL(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_EPHSR_SNGL_COL(void); static inline u_int8_t mem_get_EPHSR_SNGL_COL(u_int16_t reg_val); static inline void mem_set_EPHSR_SNGL_COL(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_EPHSR_TX_SUC(void); static inline u_int8_t mem_get_EPHSR_TX_SUC(u_int16_t reg_val); static inline void mem_set_EPHSR_TX_SUC(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_RCR(void); static inline void set_RCR(u_int16_t val); static inline u_int8_t get_RCR_SOFT_RST(void); static inline void set_RCR_SOFT_RST(u_int8_t bit_val); static inline u_int8_t mem_get_RCR_SOFT_RST(u_int16_t reg_val); static inline void mem_set_RCR_SOFT_RST(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_RCR_FILT_CAR(void); static inline void set_RCR_FILT_CAR(u_int8_t bit_val); static inline u_int8_t mem_get_RCR_FILT_CAR(u_int16_t reg_val); static inline void mem_set_RCR_FILT_CAR(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_RCR_ABORT_ENB(void); static inline void set_RCR_ABORT_ENB(u_int8_t bit_val); static inline u_int8_t mem_get_RCR_ABORT_ENB(u_int16_t reg_val); static inline void mem_set_RCR_ABORT_ENB(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_RCR_STRIP_CRC(void); static inline void set_RCR_STRIP_CRC(u_int8_t bit_val); static inline u_int8_t mem_get_RCR_STRIP_CRC(u_int16_t reg_val); static inline void mem_set_RCR_STRIP_CRC(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_RCR_RXEN(void); static inline void set_RCR_RXEN(u_int8_t bit_val); static inline u_int8_t mem_get_RCR_RXEN(u_int16_t reg_val); static inline void mem_set_RCR_RXEN(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_RCR_ALMUL(void); static inline void set_RCR_ALMUL(u_int8_t bit_val); static inline u_int8_t mem_get_RCR_ALMUL(u_int16_t reg_val); static inline void mem_set_RCR_ALMUL(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_RCR_PRMS(void); static inline void set_RCR_PRMS(u_int8_t bit_val); static inline u_int8_t mem_get_RCR_PRMS(u_int16_t reg_val); static inline void mem_set_RCR_PRMS(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_RCR_RX_ABORT(void); static inline void set_RCR_RX_ABORT(u_int8_t bit_val); static inline u_int8_t mem_get_RCR_RX_ABORT(u_int16_t reg_val); static inline void mem_set_RCR_RX_ABORT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_ECR(void); static inline u_int8_t get_ECR_EXDTX(void); static inline u_int8_t mem_get_ECR_EXDTX(u_int16_t reg_val); static inline void mem_set_ECR_EXDTX(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ECR_DTX(void); static inline u_int8_t mem_get_ECR_DTX(u_int16_t reg_val); static inline void mem_set_ECR_DTX(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ECR_MCOLN(void); static inline u_int8_t mem_get_ECR_MCOLN(u_int16_t reg_val); static inline void mem_set_ECR_MCOLN(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ECR_COLN(void); static inline u_int8_t mem_get_ECR_COLN(u_int16_t reg_val); static inline void mem_set_ECR_COLN(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_MIR(void); static inline u_int8_t get_MIR_AVAIL(void); static inline u_int8_t mem_get_MIR_AVAIL(u_int16_t reg_val); static inline void mem_set_MIR_AVAIL(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MIR_SIZE(void); static inline u_int8_t mem_get_MIR_SIZE(u_int16_t reg_val); static inline void mem_set_MIR_SIZE(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_RPCR(void); static inline void set_RPCR(u_int16_t val); static inline u_int8_t get_RPCR_SPEED(void); static inline void set_RPCR_SPEED(u_int8_t bit_val); static inline u_int8_t mem_get_RPCR_SPEED(u_int16_t reg_val); static inline void mem_set_RPCR_SPEED(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_RPCR_DPLX(void); static inline void set_RPCR_DPLX(u_int8_t bit_val); static inline u_int8_t mem_get_RPCR_DPLX(u_int16_t reg_val); static inline void mem_set_RPCR_DPLX(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_RPCR_ANEG(void); static inline void set_RPCR_ANEG(u_int8_t bit_val); static inline u_int8_t mem_get_RPCR_ANEG(u_int16_t reg_val); static inline void mem_set_RPCR_ANEG(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_RPCR_LEDA(void); static inline void set_RPCR_LEDA(u_int8_t bit_val); static inline u_int8_t mem_get_RPCR_LEDA(u_int16_t reg_val); static inline void mem_set_RPCR_LEDA(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_RPCR_LEDB(void); static inline void set_RPCR_LEDB(u_int8_t bit_val); static inline u_int8_t mem_get_RPCR_LEDB(u_int16_t reg_val); static inline void mem_set_RPCR_LEDB(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_CR(void); static inline void set_CR(u_int16_t val); static inline u_int8_t get_CR_EPH_Power_EN(void); static inline void set_CR_EPH_Power_EN(u_int8_t bit_val); static inline u_int8_t mem_get_CR_EPH_Power_EN(u_int16_t reg_val); static inline void mem_set_CR_EPH_Power_EN(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_CR_NO_WAIT(void); static inline void set_CR_NO_WAIT(u_int8_t bit_val); static inline u_int8_t mem_get_CR_NO_WAIT(u_int16_t reg_val); static inline void mem_set_CR_NO_WAIT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_CR_GPCNTRL(void); static inline void set_CR_GPCNTRL(u_int8_t bit_val); static inline u_int8_t mem_get_CR_GPCNTRL(u_int16_t reg_val); static inline void mem_set_CR_GPCNTRL(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_CR_EXT_PHY(void); static inline void set_CR_EXT_PHY(u_int8_t bit_val); static inline u_int8_t mem_get_CR_EXT_PHY(u_int16_t reg_val); static inline void mem_set_CR_EXT_PHY(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_BAR(void); static inline void set_BAR(u_int16_t val); static inline u_int8_t get_BAR_A15_13(void); static inline void set_BAR_A15_13(u_int8_t bit_val); static inline u_int8_t mem_get_BAR_A15_13(u_int16_t reg_val); static inline void mem_set_BAR_A15_13(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_BAR_A9_5(void); static inline void set_BAR_A9_5(u_int8_t bit_val); static inline u_int8_t mem_get_BAR_A9_5(u_int16_t reg_val); static inline void mem_set_BAR_A9_5(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_IAR1_0(void); static inline void set_IAR1_0(u_int16_t val); static inline u_int8_t get_IAR1_0_A1(void); static inline void set_IAR1_0_A1(u_int8_t bit_val); static inline u_int8_t mem_get_IAR1_0_A1(u_int16_t reg_val); static inline void mem_set_IAR1_0_A1(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IAR1_0_A0(void); static inline void set_IAR1_0_A0(u_int8_t bit_val); static inline u_int8_t mem_get_IAR1_0_A0(u_int16_t reg_val); static inline void mem_set_IAR1_0_A0(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_IAR3_2(void); static inline void set_IAR3_2(u_int16_t val); static inline u_int8_t get_IAR3_2_A3(void); static inline void set_IAR3_2_A3(u_int8_t bit_val); static inline u_int8_t mem_get_IAR3_2_A3(u_int16_t reg_val); static inline void mem_set_IAR3_2_A3(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IAR3_2_A2(void); static inline void set_IAR3_2_A2(u_int8_t bit_val); static inline u_int8_t mem_get_IAR3_2_A2(u_int16_t reg_val); static inline void mem_set_IAR3_2_A2(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_IAR5_4(void); static inline void set_IAR5_4(u_int16_t val); static inline u_int8_t get_IAR5_4_A5(void); static inline void set_IAR5_4_A5(u_int8_t bit_val); static inline u_int8_t mem_get_IAR5_4_A5(u_int16_t reg_val); static inline void mem_set_IAR5_4_A5(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IAR5_4_A4(void); static inline void set_IAR5_4_A4(u_int8_t bit_val); static inline u_int8_t mem_get_IAR5_4_A4(u_int16_t reg_val); static inline void mem_set_IAR5_4_A4(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_GPR(void); static inline void set_GPR(u_int16_t val); static inline u_int16_t get_GPR_DATA(void); static inline void set_GPR_DATA(u_int16_t bit_val); static inline u_int16_t mem_get_GPR_DATA(u_int16_t reg_val); static inline void mem_set_GPR_DATA(u_int16_t *reg_val, u_int16_t bit_val); static inline u_int16_t get_CTR(void); static inline void set_CTR(u_int16_t val); static inline u_int8_t get_CTR_RCV_BAD(void); static inline void set_CTR_RCV_BAD(u_int8_t bit_val); static inline u_int8_t mem_get_CTR_RCV_BAD(u_int16_t reg_val); static inline void mem_set_CTR_RCV_BAD(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_CTR_AUTO_RELEASE(void); static inline void set_CTR_AUTO_RELEASE(u_int8_t bit_val); static inline u_int8_t mem_get_CTR_AUTO_RELEASE(u_int16_t reg_val); static inline void mem_set_CTR_AUTO_RELEASE(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_CTR_LE_ENABLE(void); static inline void set_CTR_LE_ENABLE(u_int8_t bit_val); static inline u_int8_t mem_get_CTR_LE_ENABLE(u_int16_t reg_val); static inline void mem_set_CTR_LE_ENABLE(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_CTR_CR_ENABLE(void); static inline void set_CTR_CR_ENABLE(u_int8_t bit_val); static inline u_int8_t mem_get_CTR_CR_ENABLE(u_int16_t reg_val); static inline void mem_set_CTR_CR_ENABLE(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_CTR_TE_ENABLE(void); static inline void set_CTR_TE_ENABLE(u_int8_t bit_val); static inline u_int8_t mem_get_CTR_TE_ENABLE(u_int16_t reg_val); static inline void mem_set_CTR_TE_ENABLE(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_CTR_EEPROM_SELECT(void); static inline void set_CTR_EEPROM_SELECT(u_int8_t bit_val); static inline u_int8_t mem_get_CTR_EEPROM_SELECT(u_int16_t reg_val); static inline void mem_set_CTR_EEPROM_SELECT(u_int16_t *reg_val, u_int8_t bit_val); /* Warning: dont_change and volatile for register CTR bit RELOAD */ static inline u_int8_t get_CTR_RELOAD(void); static inline void set_CTR_RELOAD(u_int8_t bit_val); static inline u_int8_t mem_get_CTR_RELOAD(u_int16_t reg_val); static inline void mem_set_CTR_RELOAD(u_int16_t *reg_val, u_int8_t bit_val); /* Warning: dont_change and volatile for register CTR bit STORE */ static inline u_int8_t get_CTR_STORE(void); static inline void set_CTR_STORE(u_int8_t bit_val); static inline u_int8_t mem_get_CTR_STORE(u_int16_t reg_val); static inline void mem_set_CTR_STORE(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_MMUCR(void); static inline void set_MMUCR(u_int16_t val); static inline u_int8_t get_MMUCR_CMD(void); static inline void set_MMUCR_CMD(u_int8_t bit_val); static inline u_int8_t mem_get_MMUCR_CMD(u_int16_t reg_val); static inline void mem_set_MMUCR_CMD(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MMUCR_BUSY(void); static inline u_int8_t mem_get_MMUCR_BUSY(u_int16_t reg_val); static inline void mem_set_MMUCR_BUSY(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_PNR(void); static inline void set_PNR(u_int16_t val); static inline u_int8_t get_PNR_PACKET_NUMBER_AT_TX_AREA(void); static inline void set_PNR_PACKET_NUMBER_AT_TX_AREA(u_int8_t bit_val); static inline u_int8_t mem_get_PNR_PACKET_NUMBER_AT_TX_AREA(u_int16_t reg_val); static inline void mem_set_PNR_PACKET_NUMBER_AT_TX_AREA(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_ARR(void); static inline u_int8_t get_ARR_FAILED(void); static inline u_int8_t mem_get_ARR_FAILED(u_int16_t reg_val); static inline void mem_set_ARR_FAILED(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ARR_ALLOCATED_PACKET_NUMBER(void); static inline u_int8_t mem_get_ARR_ALLOCATED_PACKET_NUMBER(u_int16_t reg_val); static inline void mem_set_ARR_ALLOCATED_PACKET_NUMBER(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_FIFO(void); static inline u_int8_t get_FIFO_REMPTY(void); static inline u_int8_t mem_get_FIFO_REMPTY(u_int16_t reg_val); static inline void mem_set_FIFO_REMPTY(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_FIFO_RX_FIFO_PACKET_NUMBER(void); static inline u_int8_t mem_get_FIFO_RX_FIFO_PACKET_NUMBER(u_int16_t reg_val); static inline void mem_set_FIFO_RX_FIFO_PACKET_NUMBER(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_FIFO_TEMPTY(void); static inline u_int8_t mem_get_FIFO_TEMPTY(u_int16_t reg_val); static inline void mem_set_FIFO_TEMPTY(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_FIFO_TX_FIFO_PACKET_NUMBER(void); static inline u_int8_t mem_get_FIFO_TX_FIFO_PACKET_NUMBER(u_int16_t reg_val); static inline void mem_set_FIFO_TX_FIFO_PACKET_NUMBER(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_PTR(void); static inline void set_PTR(u_int16_t val); static inline u_int8_t get_PTR_RCV(void); static inline u_int8_t mem_get_PTR_RCV(u_int16_t reg_val); static inline void mem_set_PTR_RCV(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_PTR_AUTO_INCR(void); static inline u_int8_t mem_get_PTR_AUTO_INCR(u_int16_t reg_val); static inline void mem_set_PTR_AUTO_INCR(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_PTR_READ(void); static inline u_int8_t mem_get_PTR_READ(u_int16_t reg_val); static inline void mem_set_PTR_READ(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_PTR_ETEN(void); static inline u_int8_t mem_get_PTR_ETEN(u_int16_t reg_val); static inline void mem_set_PTR_ETEN(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_PTR_NOT_EMPTY(void); static inline u_int8_t mem_get_PTR_NOT_EMPTY(u_int16_t reg_val); static inline void mem_set_PTR_NOT_EMPTY(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_PTR_POINTER_HIGH(void); static inline u_int8_t mem_get_PTR_POINTER_HIGH(u_int16_t reg_val); static inline void mem_set_PTR_POINTER_HIGH(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_PTR_POINTER_LOW(void); static inline u_int8_t mem_get_PTR_POINTER_LOW(u_int16_t reg_val); static inline void mem_set_PTR_POINTER_LOW(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_DATA(void); static inline void set_DATA(u_int16_t val); static inline u_int16_t get_DATA_DATA(void); static inline void set_DATA_DATA(u_int16_t bit_val); static inline u_int16_t mem_get_DATA_DATA(u_int16_t reg_val); static inline void mem_set_DATA_DATA(u_int16_t *reg_val, u_int16_t bit_val); static inline u_int16_t get_IST(void); static inline u_int8_t get_IST_MDINT(void); static inline u_int8_t mem_get_IST_MDINT(u_int16_t reg_val); static inline void mem_set_IST_MDINT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IST_ERCV_INT(void); static inline u_int8_t mem_get_IST_ERCV_INT(u_int16_t reg_val); static inline void mem_set_IST_ERCV_INT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IST_EPH_INT(void); static inline u_int8_t mem_get_IST_EPH_INT(u_int16_t reg_val); static inline void mem_set_IST_EPH_INT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IST_RX_OVRN_INT(void); static inline u_int8_t mem_get_IST_RX_OVRN_INT(u_int16_t reg_val); static inline void mem_set_IST_RX_OVRN_INT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IST_ALLOC_INT(void); static inline u_int8_t mem_get_IST_ALLOC_INT(u_int16_t reg_val); static inline void mem_set_IST_ALLOC_INT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IST_TX_EMPTY_INT(void); static inline u_int8_t mem_get_IST_TX_EMPTY_INT(u_int16_t reg_val); static inline void mem_set_IST_TX_EMPTY_INT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IST_TX_INT(void); static inline u_int8_t mem_get_IST_TX_INT(u_int16_t reg_val); static inline void mem_set_IST_TX_INT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_IST_RCV_INT(void); static inline u_int8_t mem_get_IST_RCV_INT(u_int16_t reg_val); static inline void mem_set_IST_RCV_INT(u_int16_t *reg_val, u_int8_t bit_val); static inline void set_ACK(u_int16_t val); static inline u_int8_t mem_get_ACK_MDINT(u_int16_t reg_val); static inline void mem_set_ACK_MDINT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t mem_get_ACK_ERCV_INT(u_int16_t reg_val); static inline void mem_set_ACK_ERCV_INT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t mem_get_ACK_RX_OVRN_INT(u_int16_t reg_val); static inline void mem_set_ACK_RX_OVRN_INT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t mem_get_ACK_TX_EMPTY_INT(u_int16_t reg_val); static inline void mem_set_ACK_TX_EMPTY_INT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t mem_get_ACK_TX_INT(u_int16_t reg_val); static inline void mem_set_ACK_TX_INT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_MSK(void); static inline void set_MSK(u_int16_t val); static inline u_int8_t get_MSK_MDINT(void); static inline void set_MSK_MDINT(u_int8_t bit_val); static inline u_int8_t mem_get_MSK_MDINT(u_int16_t reg_val); static inline void mem_set_MSK_MDINT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MSK_ERCV_INT(void); static inline void set_MSK_ERCV_INT(u_int8_t bit_val); static inline u_int8_t mem_get_MSK_ERCV_INT(u_int16_t reg_val); static inline void mem_set_MSK_ERCV_INT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MSK_EPH_INT(void); static inline void set_MSK_EPH_INT(u_int8_t bit_val); static inline u_int8_t mem_get_MSK_EPH_INT(u_int16_t reg_val); static inline void mem_set_MSK_EPH_INT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MSK_RX_OVRN_INT(void); static inline void set_MSK_RX_OVRN_INT(u_int8_t bit_val); static inline u_int8_t mem_get_MSK_RX_OVRN_INT(u_int16_t reg_val); static inline void mem_set_MSK_RX_OVRN_INT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MSK_ALLOC_INT(void); static inline void set_MSK_ALLOC_INT(u_int8_t bit_val); static inline u_int8_t mem_get_MSK_ALLOC_INT(u_int16_t reg_val); static inline void mem_set_MSK_ALLOC_INT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MSK_TX_EMPTY_INT(void); static inline void set_MSK_TX_EMPTY_INT(u_int8_t bit_val); static inline u_int8_t mem_get_MSK_TX_EMPTY_INT(u_int16_t reg_val); static inline void mem_set_MSK_TX_EMPTY_INT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MSK_TX_INT(void); static inline void set_MSK_TX_INT(u_int8_t bit_val); static inline u_int8_t mem_get_MSK_TX_INT(u_int16_t reg_val); static inline void mem_set_MSK_TX_INT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MSK_RCV_INT(void); static inline void set_MSK_RCV_INT(u_int8_t bit_val); static inline u_int8_t mem_get_MSK_RCV_INT(u_int16_t reg_val); static inline void mem_set_MSK_RCV_INT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_MT1_0(void); static inline void set_MT1_0(u_int16_t val); static inline u_int8_t get_MT1_0_MT1(void); static inline void set_MT1_0_MT1(u_int8_t bit_val); static inline u_int8_t mem_get_MT1_0_MT1(u_int16_t reg_val); static inline void mem_set_MT1_0_MT1(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MT1_0_MT0(void); static inline void set_MT1_0_MT0(u_int8_t bit_val); static inline u_int8_t mem_get_MT1_0_MT0(u_int16_t reg_val); static inline void mem_set_MT1_0_MT0(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_MT3_2(void); static inline void set_MT3_2(u_int16_t val); static inline u_int8_t get_MT3_2_MT3(void); static inline void set_MT3_2_MT3(u_int8_t bit_val); static inline u_int8_t mem_get_MT3_2_MT3(u_int16_t reg_val); static inline void mem_set_MT3_2_MT3(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MT3_2_MT2(void); static inline void set_MT3_2_MT2(u_int8_t bit_val); static inline u_int8_t mem_get_MT3_2_MT2(u_int16_t reg_val); static inline void mem_set_MT3_2_MT2(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_MT5_4(void); static inline void set_MT5_4(u_int16_t val); static inline u_int8_t get_MT5_4_MT5(void); static inline void set_MT5_4_MT5(u_int8_t bit_val); static inline u_int8_t mem_get_MT5_4_MT5(u_int16_t reg_val); static inline void mem_set_MT5_4_MT5(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MT5_4_MT4(void); static inline void set_MT5_4_MT4(u_int8_t bit_val); static inline u_int8_t mem_get_MT5_4_MT4(u_int16_t reg_val); static inline void mem_set_MT5_4_MT4(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_MT7_6(void); static inline void set_MT7_6(u_int16_t val); static inline u_int8_t get_MT7_6_MT7(void); static inline void set_MT7_6_MT7(u_int8_t bit_val); static inline u_int8_t mem_get_MT7_6_MT7(u_int16_t reg_val); static inline void mem_set_MT7_6_MT7(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MT7_6_MT6(void); static inline void set_MT7_6_MT6(u_int8_t bit_val); static inline u_int8_t mem_get_MT7_6_MT6(u_int16_t reg_val); static inline void mem_set_MT7_6_MT6(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_MGMT(void); static inline void set_MGMT(u_int16_t val); static inline u_int8_t get_MGMT_MSK_CRS100(void); static inline u_int8_t mem_get_MGMT_MSK_CRS100(u_int16_t reg_val); static inline void mem_set_MGMT_MSK_CRS100(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MGMT_MDOE(void); static inline u_int8_t mem_get_MGMT_MDOE(u_int16_t reg_val); static inline void mem_set_MGMT_MDOE(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MGMT_MCLK(void); static inline u_int8_t mem_get_MGMT_MCLK(u_int16_t reg_val); static inline void mem_set_MGMT_MCLK(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MGMT_MDIN(void); static inline u_int8_t mem_get_MGMT_MDIN(u_int16_t reg_val); static inline void mem_set_MGMT_MDIN(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_MGMT_MDOUT(void); static inline u_int8_t mem_get_MGMT_MDOUT(u_int16_t reg_val); static inline void mem_set_MGMT_MDOUT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_REV(void); static inline u_int8_t get_REV_CHIP(void); static inline u_int8_t mem_get_REV_CHIP(u_int16_t reg_val); static inline void mem_set_REV_CHIP(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_REV_REV(void); static inline u_int8_t mem_get_REV_REV(u_int16_t reg_val); static inline void mem_set_REV_REV(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_ERCV(void); static inline void set_ERCV(u_int16_t val); static inline u_int8_t get_ERCV_RCV_DISCRD(void); static inline u_int8_t mem_get_ERCV_RCV_DISCRD(u_int16_t reg_val); static inline void mem_set_ERCV_RCV_DISCRD(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ERCV_ERCV_THRESHOLD(void); static inline u_int8_t mem_get_ERCV_ERCV_THRESHOLD(u_int16_t reg_val); static inline void mem_set_ERCV_ERCV_THRESHOLD(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_Control(void); static inline void set_Control(u_int16_t val); /* Warning: dont_change and volatile for register Control bit RST */ static inline u_int8_t get_Control_RST(void); static inline void set_Control_RST(u_int8_t bit_val); static inline u_int8_t mem_get_Control_RST(u_int16_t reg_val); static inline void mem_set_Control_RST(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Control_LPBK(void); static inline void set_Control_LPBK(u_int8_t bit_val); static inline u_int8_t mem_get_Control_LPBK(u_int16_t reg_val); static inline void mem_set_Control_LPBK(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Control_SPEED(void); static inline void set_Control_SPEED(u_int8_t bit_val); static inline u_int8_t mem_get_Control_SPEED(u_int16_t reg_val); static inline void mem_set_Control_SPEED(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Control_ANEG_EN(void); static inline void set_Control_ANEG_EN(u_int8_t bit_val); static inline u_int8_t mem_get_Control_ANEG_EN(u_int16_t reg_val); static inline void mem_set_Control_ANEG_EN(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Control_PDN(void); static inline void set_Control_PDN(u_int8_t bit_val); static inline u_int8_t mem_get_Control_PDN(u_int16_t reg_val); static inline void mem_set_Control_PDN(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Control_MII_DIS(void); static inline void set_Control_MII_DIS(u_int8_t bit_val); static inline u_int8_t mem_get_Control_MII_DIS(u_int16_t reg_val); static inline void mem_set_Control_MII_DIS(u_int16_t *reg_val, u_int8_t bit_val); /* Warning: dont_change and volatile for register Control bit ANEG_RST */ static inline u_int8_t get_Control_ANEG_RST(void); static inline void set_Control_ANEG_RST(u_int8_t bit_val); static inline u_int8_t mem_get_Control_ANEG_RST(u_int16_t reg_val); static inline void mem_set_Control_ANEG_RST(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Control_DPLX(void); static inline void set_Control_DPLX(u_int8_t bit_val); static inline u_int8_t mem_get_Control_DPLX(u_int16_t reg_val); static inline void mem_set_Control_DPLX(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Control_COLST(void); static inline void set_Control_COLST(u_int8_t bit_val); static inline u_int8_t mem_get_Control_COLST(u_int16_t reg_val); static inline void mem_set_Control_COLST(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_Status(void); static inline u_int8_t get_Status_CAP_T4(void); static inline u_int8_t mem_get_Status_CAP_T4(u_int16_t reg_val); static inline void mem_set_Status_CAP_T4(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_CAP_TXF(void); static inline u_int8_t mem_get_Status_CAP_TXF(u_int16_t reg_val); static inline void mem_set_Status_CAP_TXF(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_CAP_TXH(void); static inline u_int8_t mem_get_Status_CAP_TXH(u_int16_t reg_val); static inline void mem_set_Status_CAP_TXH(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_CAP_TF(void); static inline u_int8_t mem_get_Status_CAP_TF(u_int16_t reg_val); static inline void mem_set_Status_CAP_TF(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_CAP_TH(void); static inline u_int8_t mem_get_Status_CAP_TH(u_int16_t reg_val); static inline void mem_set_Status_CAP_TH(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_CAP_SUPR(void); static inline u_int8_t mem_get_Status_CAP_SUPR(u_int16_t reg_val); static inline void mem_set_Status_CAP_SUPR(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_ANEG_ACK(void); static inline u_int8_t mem_get_Status_ANEG_ACK(u_int16_t reg_val); static inline void mem_set_Status_ANEG_ACK(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_REM_FLT(void); static inline u_int8_t mem_get_Status_REM_FLT(u_int16_t reg_val); static inline void mem_set_Status_REM_FLT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_CAP_ANEG(void); static inline u_int8_t mem_get_Status_CAP_ANEG(u_int16_t reg_val); static inline void mem_set_Status_CAP_ANEG(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_LINK(void); static inline u_int8_t mem_get_Status_LINK(u_int16_t reg_val); static inline void mem_set_Status_LINK(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_JAB(void); static inline u_int8_t mem_get_Status_JAB(u_int16_t reg_val); static inline void mem_set_Status_JAB(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_EXREG(void); static inline u_int8_t mem_get_Status_EXREG(u_int16_t reg_val); static inline void mem_set_Status_EXREG(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_PHY_ID1(void); static inline u_int16_t get_PHY_ID1_VENDOR(void); static inline u_int16_t mem_get_PHY_ID1_VENDOR(u_int16_t reg_val); static inline void mem_set_PHY_ID1_VENDOR(u_int16_t *reg_val, u_int16_t bit_val); static inline u_int16_t get_PHY_ID2(void); static inline u_int8_t get_PHY_ID2_OUILSB(void); static inline u_int8_t mem_get_PHY_ID2_OUILSB(u_int16_t reg_val); static inline void mem_set_PHY_ID2_OUILSB(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_PHY_ID2_MFGR(void); static inline u_int8_t mem_get_PHY_ID2_MFGR(u_int16_t reg_val); static inline void mem_set_PHY_ID2_MFGR(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_PHY_ID2_REV(void); static inline u_int8_t mem_get_PHY_ID2_REV(u_int16_t reg_val); static inline void mem_set_PHY_ID2_REV(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_ANA(void); static inline void set_ANA(u_int16_t val); static inline u_int8_t get_ANA_NP(void); static inline u_int8_t mem_get_ANA_NP(u_int16_t reg_val); static inline void mem_set_ANA_NP(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ANA_ACK(void); static inline u_int8_t mem_get_ANA_ACK(u_int16_t reg_val); static inline void mem_set_ANA_ACK(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ANA_RF(void); static inline u_int8_t mem_get_ANA_RF(u_int16_t reg_val); static inline void mem_set_ANA_RF(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ANA_T4(void); static inline u_int8_t mem_get_ANA_T4(u_int16_t reg_val); static inline void mem_set_ANA_T4(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ANA_TX_FDX(void); static inline u_int8_t mem_get_ANA_TX_FDX(u_int16_t reg_val); static inline void mem_set_ANA_TX_FDX(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ANA_TX_HDX(void); static inline u_int8_t mem_get_ANA_TX_HDX(u_int16_t reg_val); static inline void mem_set_ANA_TX_HDX(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ANA_TEN_FDX(void); static inline u_int8_t mem_get_ANA_TEN_FDX(u_int16_t reg_val); static inline void mem_set_ANA_TEN_FDX(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ANA_TEN_HDX(void); static inline u_int8_t mem_get_ANA_TEN_HDX(u_int16_t reg_val); static inline void mem_set_ANA_TEN_HDX(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ANA_CSMA(void); static inline u_int8_t mem_get_ANA_CSMA(u_int16_t reg_val); static inline void mem_set_ANA_CSMA(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_ANREC(void); static inline u_int8_t get_ANREC_NP(void); static inline u_int8_t mem_get_ANREC_NP(u_int16_t reg_val); static inline void mem_set_ANREC_NP(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ANREC_ACK(void); static inline u_int8_t mem_get_ANREC_ACK(u_int16_t reg_val); static inline void mem_set_ANREC_ACK(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ANREC_RF(void); static inline u_int8_t mem_get_ANREC_RF(u_int16_t reg_val); static inline void mem_set_ANREC_RF(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ANREC_T4(void); static inline u_int8_t mem_get_ANREC_T4(u_int16_t reg_val); static inline void mem_set_ANREC_T4(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ANREC_TX_FDX(void); static inline u_int8_t mem_get_ANREC_TX_FDX(u_int16_t reg_val); static inline void mem_set_ANREC_TX_FDX(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ANREC_TX_HDX(void); static inline u_int8_t mem_get_ANREC_TX_HDX(u_int16_t reg_val); static inline void mem_set_ANREC_TX_HDX(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ANREC_TEN_FDX(void); static inline u_int8_t mem_get_ANREC_TEN_FDX(u_int16_t reg_val); static inline void mem_set_ANREC_TEN_FDX(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ANREC_TEN_HDX(void); static inline u_int8_t mem_get_ANREC_TEN_HDX(u_int16_t reg_val); static inline void mem_set_ANREC_TEN_HDX(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_ANREC_CSMA(void); static inline u_int8_t mem_get_ANREC_CSMA(u_int16_t reg_val); static inline void mem_set_ANREC_CSMA(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_Config1(void); static inline void set_Config1(u_int16_t val); static inline u_int8_t get_Config1_LNKDIS(void); static inline void set_Config1_LNKDIS(u_int8_t bit_val); static inline u_int8_t mem_get_Config1_LNKDIS(u_int16_t reg_val); static inline void mem_set_Config1_LNKDIS(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Config1_XMTDIS(void); static inline void set_Config1_XMTDIS(u_int8_t bit_val); static inline u_int8_t mem_get_Config1_XMTDIS(u_int16_t reg_val); static inline void mem_set_Config1_XMTDIS(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Config1_XMTPDN(void); static inline void set_Config1_XMTPDN(u_int8_t bit_val); static inline u_int8_t mem_get_Config1_XMTPDN(u_int16_t reg_val); static inline void mem_set_Config1_XMTPDN(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Config1_BYPSCR(void); static inline void set_Config1_BYPSCR(u_int8_t bit_val); static inline u_int8_t mem_get_Config1_BYPSCR(u_int16_t reg_val); static inline void mem_set_Config1_BYPSCR(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Config1_UNSCDS(void); static inline void set_Config1_UNSCDS(u_int8_t bit_val); static inline u_int8_t mem_get_Config1_UNSCDS(u_int16_t reg_val); static inline void mem_set_Config1_UNSCDS(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Config1_EQLZR(void); static inline void set_Config1_EQLZR(u_int8_t bit_val); static inline u_int8_t mem_get_Config1_EQLZR(u_int16_t reg_val); static inline void mem_set_Config1_EQLZR(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Config1_CABLE(void); static inline void set_Config1_CABLE(u_int8_t bit_val); static inline u_int8_t mem_get_Config1_CABLE(u_int16_t reg_val); static inline void mem_set_Config1_CABLE(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Config1_RLVL(void); static inline void set_Config1_RLVL(u_int8_t bit_val); static inline u_int8_t mem_get_Config1_RLVL(u_int16_t reg_val); static inline void mem_set_Config1_RLVL(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Config1_TLVL(void); static inline void set_Config1_TLVL(u_int8_t bit_val); static inline u_int8_t mem_get_Config1_TLVL(u_int16_t reg_val); static inline void mem_set_Config1_TLVL(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Config1_TRF(void); static inline void set_Config1_TRF(u_int8_t bit_val); static inline u_int8_t mem_get_Config1_TRF(u_int16_t reg_val); static inline void mem_set_Config1_TRF(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_Config2(void); static inline void set_Config2(u_int16_t val); static inline u_int8_t get_Config2_APOLDIS(void); static inline void set_Config2_APOLDIS(u_int8_t bit_val); static inline u_int8_t mem_get_Config2_APOLDIS(u_int16_t reg_val); static inline void mem_set_Config2_APOLDIS(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Config2_JABDIS(void); static inline void set_Config2_JABDIS(u_int8_t bit_val); static inline u_int8_t mem_get_Config2_JABDIS(u_int16_t reg_val); static inline void mem_set_Config2_JABDIS(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Config2_MREG(void); static inline void set_Config2_MREG(u_int8_t bit_val); static inline u_int8_t mem_get_Config2_MREG(u_int16_t reg_val); static inline void mem_set_Config2_MREG(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Config2_INTMDIO(void); static inline void set_Config2_INTMDIO(u_int8_t bit_val); static inline u_int8_t mem_get_Config2_INTMDIO(u_int16_t reg_val); static inline void mem_set_Config2_INTMDIO(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_Status_Output(void); static inline u_int8_t get_Status_Output_INT(void); static inline u_int8_t mem_get_Status_Output_INT(u_int16_t reg_val); static inline void mem_set_Status_Output_INT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_Output_LNKFAIL(void); static inline u_int8_t mem_get_Status_Output_LNKFAIL(u_int16_t reg_val); static inline void mem_set_Status_Output_LNKFAIL(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_Output_LOSSSYNC(void); static inline u_int8_t mem_get_Status_Output_LOSSSYNC(u_int16_t reg_val); static inline void mem_set_Status_Output_LOSSSYNC(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_Output_CWRD(void); static inline u_int8_t mem_get_Status_Output_CWRD(u_int16_t reg_val); static inline void mem_set_Status_Output_CWRD(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_Output_SSD(void); static inline u_int8_t mem_get_Status_Output_SSD(u_int16_t reg_val); static inline void mem_set_Status_Output_SSD(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_Output_ESD(void); static inline u_int8_t mem_get_Status_Output_ESD(u_int16_t reg_val); static inline void mem_set_Status_Output_ESD(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_Output_RPOL(void); static inline u_int8_t mem_get_Status_Output_RPOL(u_int16_t reg_val); static inline void mem_set_Status_Output_RPOL(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_Output_JAB(void); static inline u_int8_t mem_get_Status_Output_JAB(u_int16_t reg_val); static inline void mem_set_Status_Output_JAB(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_Output_SPDDET(void); static inline u_int8_t mem_get_Status_Output_SPDDET(u_int16_t reg_val); static inline void mem_set_Status_Output_SPDDET(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Status_Output_DPLXDET(void); static inline u_int8_t mem_get_Status_Output_DPLXDET(u_int16_t reg_val); static inline void mem_set_Status_Output_DPLXDET(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_Mask(void); static inline void set_Mask(u_int16_t val); static inline u_int8_t get_Mask_MINT(void); static inline void set_Mask_MINT(u_int8_t bit_val); static inline u_int8_t mem_get_Mask_MINT(u_int16_t reg_val); static inline void mem_set_Mask_MINT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Mask_MLNKFAIL(void); static inline void set_Mask_MLNKFAIL(u_int8_t bit_val); static inline u_int8_t mem_get_Mask_MLNKFAIL(u_int16_t reg_val); static inline void mem_set_Mask_MLNKFAIL(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Mask_MLOSSSYN(void); static inline void set_Mask_MLOSSSYN(u_int8_t bit_val); static inline u_int8_t mem_get_Mask_MLOSSSYN(u_int16_t reg_val); static inline void mem_set_Mask_MLOSSSYN(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Mask_MCWRD(void); static inline void set_Mask_MCWRD(u_int8_t bit_val); static inline u_int8_t mem_get_Mask_MCWRD(u_int16_t reg_val); static inline void mem_set_Mask_MCWRD(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Mask_MSSD(void); static inline void set_Mask_MSSD(u_int8_t bit_val); static inline u_int8_t mem_get_Mask_MSSD(u_int16_t reg_val); static inline void mem_set_Mask_MSSD(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Mask_MESD(void); static inline void set_Mask_MESD(u_int8_t bit_val); static inline u_int8_t mem_get_Mask_MESD(u_int16_t reg_val); static inline void mem_set_Mask_MESD(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Mask_MRPOL(void); static inline void set_Mask_MRPOL(u_int8_t bit_val); static inline u_int8_t mem_get_Mask_MRPOL(u_int16_t reg_val); static inline void mem_set_Mask_MRPOL(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Mask_MJAB(void); static inline void set_Mask_MJAB(u_int8_t bit_val); static inline u_int8_t mem_get_Mask_MJAB(u_int16_t reg_val); static inline void mem_set_Mask_MJAB(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Mask_MSPDDT(void); static inline void set_Mask_MSPDDT(u_int8_t bit_val); static inline u_int8_t mem_get_Mask_MSPDDT(u_int16_t reg_val); static inline void mem_set_Mask_MSPDDT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int8_t get_Mask_MDPLDT(void); static inline void set_Mask_MDPLDT(u_int8_t bit_val); static inline u_int8_t mem_get_Mask_MDPLDT(u_int16_t reg_val); static inline void mem_set_Mask_MDPLDT(u_int16_t *reg_val, u_int8_t bit_val); static inline u_int16_t get_Reserved(void); static inline void set_Reserved(u_int16_t val); /* raw register access */ static inline u_int16_t _raw_read_BSR(void); static inline u_int16_t _raw_read_BSR(void){ return *(volatile u_int16_t*)(smc91_base + 14); } static inline void _raw_write_BSR(u_int16_t val); static inline void _raw_write_BSR(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 14) = val; } static inline u_int8_t _raw_read_BSR_ID(void); static inline u_int8_t _raw_read_BSR_ID(void){ return (_raw_read_BSR() & BSR_ID_MASK) >> BSR_ID_SHIFT; } static inline u_int8_t _raw_read_BSR_BANK(void); static inline u_int8_t _raw_read_BSR_BANK(void){ return (_raw_read_BSR() & BSR_BANK_MASK) >> BSR_BANK_SHIFT; } static inline u_int16_t _raw_read_TCR(void); static inline u_int16_t _raw_read_TCR(void){ return *(volatile u_int16_t*)(smc91_base + 0); } static inline void _raw_write_TCR(u_int16_t val); static inline void _raw_write_TCR(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 0) = val; } static inline u_int8_t _raw_read_TCR_SWFDUP(void); static inline u_int8_t _raw_read_TCR_SWFDUP(void){ return (_raw_read_TCR() & TCR_SWFDUP_MASK) >> TCR_SWFDUP_SHIFT; } static inline u_int8_t _raw_read_TCR_EPH_LOOP(void); static inline u_int8_t _raw_read_TCR_EPH_LOOP(void){ return (_raw_read_TCR() & TCR_EPH_LOOP_MASK) >> TCR_EPH_LOOP_SHIFT; } static inline u_int8_t _raw_read_TCR_STP_SQET(void); static inline u_int8_t _raw_read_TCR_STP_SQET(void){ return (_raw_read_TCR() & TCR_STP_SQET_MASK) >> TCR_STP_SQET_SHIFT; } static inline u_int8_t _raw_read_TCR_FDUPLX(void); static inline u_int8_t _raw_read_TCR_FDUPLX(void){ return (_raw_read_TCR() & TCR_FDUPLX_MASK) >> TCR_FDUPLX_SHIFT; } static inline u_int8_t _raw_read_TCR_MON_CSN(void); static inline u_int8_t _raw_read_TCR_MON_CSN(void){ return (_raw_read_TCR() & TCR_MON_CSN_MASK) >> TCR_MON_CSN_SHIFT; } static inline u_int8_t _raw_read_TCR_NOCRC(void); static inline u_int8_t _raw_read_TCR_NOCRC(void){ return (_raw_read_TCR() & TCR_NOCRC_MASK) >> TCR_NOCRC_SHIFT; } static inline u_int8_t _raw_read_TCR_PAD_EN(void); static inline u_int8_t _raw_read_TCR_PAD_EN(void){ return (_raw_read_TCR() & TCR_PAD_EN_MASK) >> TCR_PAD_EN_SHIFT; } static inline u_int8_t _raw_read_TCR_FORCOL(void); static inline u_int8_t _raw_read_TCR_FORCOL(void){ return (_raw_read_TCR() & TCR_FORCOL_MASK) >> TCR_FORCOL_SHIFT; } static inline u_int8_t _raw_read_TCR_LOOP(void); static inline u_int8_t _raw_read_TCR_LOOP(void){ return (_raw_read_TCR() & TCR_LOOP_MASK) >> TCR_LOOP_SHIFT; } static inline u_int8_t _raw_read_TCR_TXENA(void); static inline u_int8_t _raw_read_TCR_TXENA(void){ return (_raw_read_TCR() & TCR_TXENA_MASK) >> TCR_TXENA_SHIFT; } static inline u_int16_t _raw_read_EPHSR(void); static inline u_int16_t _raw_read_EPHSR(void){ return *(volatile u_int16_t*)(smc91_base + 2); } static inline u_int8_t _raw_read_EPHSR_TX_UNRN(void); static inline u_int8_t _raw_read_EPHSR_TX_UNRN(void){ return (_raw_read_EPHSR() & EPHSR_TX_UNRN_MASK) >> EPHSR_TX_UNRN_SHIFT; } static inline u_int8_t _raw_read_EPHSR_LINK_OK(void); static inline u_int8_t _raw_read_EPHSR_LINK_OK(void){ return (_raw_read_EPHSR() & EPHSR_LINK_OK_MASK) >> EPHSR_LINK_OK_SHIFT; } static inline u_int8_t _raw_read_EPHSR_CTR_ROL(void); static inline u_int8_t _raw_read_EPHSR_CTR_ROL(void){ return (_raw_read_EPHSR() & EPHSR_CTR_ROL_MASK) >> EPHSR_CTR_ROL_SHIFT; } static inline u_int8_t _raw_read_EPHSR_EXC_DEF(void); static inline u_int8_t _raw_read_EPHSR_EXC_DEF(void){ return (_raw_read_EPHSR() & EPHSR_EXC_DEF_MASK) >> EPHSR_EXC_DEF_SHIFT; } static inline u_int8_t _raw_read_EPHSR_LOST_CAR(void); static inline u_int8_t _raw_read_EPHSR_LOST_CAR(void){ return (_raw_read_EPHSR() & EPHSR_LOST_CAR_MASK) >> EPHSR_LOST_CAR_SHIFT; } static inline u_int8_t _raw_read_EPHSR_LATCOL(void); static inline u_int8_t _raw_read_EPHSR_LATCOL(void){ return (_raw_read_EPHSR() & EPHSR_LATCOL_MASK) >> EPHSR_LATCOL_SHIFT; } static inline u_int8_t _raw_read_EPHSR_TX_DEFR(void); static inline u_int8_t _raw_read_EPHSR_TX_DEFR(void){ return (_raw_read_EPHSR() & EPHSR_TX_DEFR_MASK) >> EPHSR_TX_DEFR_SHIFT; } static inline u_int8_t _raw_read_EPHSR_LTX_BRD(void); static inline u_int8_t _raw_read_EPHSR_LTX_BRD(void){ return (_raw_read_EPHSR() & EPHSR_LTX_BRD_MASK) >> EPHSR_LTX_BRD_SHIFT; } static inline u_int8_t _raw_read_EPHSR_SQET(void); static inline u_int8_t _raw_read_EPHSR_SQET(void){ return (_raw_read_EPHSR() & EPHSR_SQET_MASK) >> EPHSR_SQET_SHIFT; } static inline u_int8_t _raw_read_EPHSR_COL16(void); static inline u_int8_t _raw_read_EPHSR_COL16(void){ return (_raw_read_EPHSR() & EPHSR_COL16_MASK) >> EPHSR_COL16_SHIFT; } static inline u_int8_t _raw_read_EPHSR_LTX_MULT(void); static inline u_int8_t _raw_read_EPHSR_LTX_MULT(void){ return (_raw_read_EPHSR() & EPHSR_LTX_MULT_MASK) >> EPHSR_LTX_MULT_SHIFT; } static inline u_int8_t _raw_read_EPHSR_MUL_COL(void); static inline u_int8_t _raw_read_EPHSR_MUL_COL(void){ return (_raw_read_EPHSR() & EPHSR_MUL_COL_MASK) >> EPHSR_MUL_COL_SHIFT; } static inline u_int8_t _raw_read_EPHSR_SNGL_COL(void); static inline u_int8_t _raw_read_EPHSR_SNGL_COL(void){ return (_raw_read_EPHSR() & EPHSR_SNGL_COL_MASK) >> EPHSR_SNGL_COL_SHIFT; } static inline u_int8_t _raw_read_EPHSR_TX_SUC(void); static inline u_int8_t _raw_read_EPHSR_TX_SUC(void){ return (_raw_read_EPHSR() & EPHSR_TX_SUC_MASK) >> EPHSR_TX_SUC_SHIFT; } static inline u_int16_t _raw_read_RCR(void); static inline u_int16_t _raw_read_RCR(void){ return *(volatile u_int16_t*)(smc91_base + 4); } static inline void _raw_write_RCR(u_int16_t val); static inline void _raw_write_RCR(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 4) = val; } static inline u_int8_t _raw_read_RCR_SOFT_RST(void); static inline u_int8_t _raw_read_RCR_SOFT_RST(void){ return (_raw_read_RCR() & RCR_SOFT_RST_MASK) >> RCR_SOFT_RST_SHIFT; } static inline u_int8_t _raw_read_RCR_FILT_CAR(void); static inline u_int8_t _raw_read_RCR_FILT_CAR(void){ return (_raw_read_RCR() & RCR_FILT_CAR_MASK) >> RCR_FILT_CAR_SHIFT; } static inline u_int8_t _raw_read_RCR_ABORT_ENB(void); static inline u_int8_t _raw_read_RCR_ABORT_ENB(void){ return (_raw_read_RCR() & RCR_ABORT_ENB_MASK) >> RCR_ABORT_ENB_SHIFT; } static inline u_int8_t _raw_read_RCR_STRIP_CRC(void); static inline u_int8_t _raw_read_RCR_STRIP_CRC(void){ return (_raw_read_RCR() & RCR_STRIP_CRC_MASK) >> RCR_STRIP_CRC_SHIFT; } static inline u_int8_t _raw_read_RCR_RXEN(void); static inline u_int8_t _raw_read_RCR_RXEN(void){ return (_raw_read_RCR() & RCR_RXEN_MASK) >> RCR_RXEN_SHIFT; } static inline u_int8_t _raw_read_RCR_ALMUL(void); static inline u_int8_t _raw_read_RCR_ALMUL(void){ return (_raw_read_RCR() & RCR_ALMUL_MASK) >> RCR_ALMUL_SHIFT; } static inline u_int8_t _raw_read_RCR_PRMS(void); static inline u_int8_t _raw_read_RCR_PRMS(void){ return (_raw_read_RCR() & RCR_PRMS_MASK) >> RCR_PRMS_SHIFT; } static inline u_int8_t _raw_read_RCR_RX_ABORT(void); static inline u_int8_t _raw_read_RCR_RX_ABORT(void){ return (_raw_read_RCR() & RCR_RX_ABORT_MASK) >> RCR_RX_ABORT_SHIFT; } static inline u_int16_t _raw_read_ECR(void); static inline u_int16_t _raw_read_ECR(void){ return *(volatile u_int16_t*)(smc91_base + 6); } static inline u_int8_t _raw_read_ECR_EXDTX(void); static inline u_int8_t _raw_read_ECR_EXDTX(void){ return (_raw_read_ECR() & ECR_EXDTX_MASK) >> ECR_EXDTX_SHIFT; } static inline u_int8_t _raw_read_ECR_DTX(void); static inline u_int8_t _raw_read_ECR_DTX(void){ return (_raw_read_ECR() & ECR_DTX_MASK) >> ECR_DTX_SHIFT; } static inline u_int8_t _raw_read_ECR_MCOLN(void); static inline u_int8_t _raw_read_ECR_MCOLN(void){ return (_raw_read_ECR() & ECR_MCOLN_MASK) >> ECR_MCOLN_SHIFT; } static inline u_int8_t _raw_read_ECR_COLN(void); static inline u_int8_t _raw_read_ECR_COLN(void){ return (_raw_read_ECR() & ECR_COLN_MASK) >> ECR_COLN_SHIFT; } static inline u_int16_t _raw_read_MIR(void); static inline u_int16_t _raw_read_MIR(void){ return *(volatile u_int16_t*)(smc91_base + 8); } static inline u_int8_t _raw_read_MIR_AVAIL(void); static inline u_int8_t _raw_read_MIR_AVAIL(void){ return (_raw_read_MIR() & MIR_AVAIL_MASK) >> MIR_AVAIL_SHIFT; } static inline u_int8_t _raw_read_MIR_SIZE(void); static inline u_int8_t _raw_read_MIR_SIZE(void){ return (_raw_read_MIR() & MIR_SIZE_MASK) >> MIR_SIZE_SHIFT; } static inline u_int16_t _raw_read_RPCR(void); static inline u_int16_t _raw_read_RPCR(void){ return *(volatile u_int16_t*)(smc91_base + 10); } static inline void _raw_write_RPCR(u_int16_t val); static inline void _raw_write_RPCR(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 10) = val; } static inline u_int8_t _raw_read_RPCR_SPEED(void); static inline u_int8_t _raw_read_RPCR_SPEED(void){ return (_raw_read_RPCR() & RPCR_SPEED_MASK) >> RPCR_SPEED_SHIFT; } static inline u_int8_t _raw_read_RPCR_DPLX(void); static inline u_int8_t _raw_read_RPCR_DPLX(void){ return (_raw_read_RPCR() & RPCR_DPLX_MASK) >> RPCR_DPLX_SHIFT; } static inline u_int8_t _raw_read_RPCR_ANEG(void); static inline u_int8_t _raw_read_RPCR_ANEG(void){ return (_raw_read_RPCR() & RPCR_ANEG_MASK) >> RPCR_ANEG_SHIFT; } static inline u_int8_t _raw_read_RPCR_LEDA(void); static inline u_int8_t _raw_read_RPCR_LEDA(void){ return (_raw_read_RPCR() & RPCR_LEDA_MASK) >> RPCR_LEDA_SHIFT; } static inline u_int8_t _raw_read_RPCR_LEDB(void); static inline u_int8_t _raw_read_RPCR_LEDB(void){ return (_raw_read_RPCR() & RPCR_LEDB_MASK) >> RPCR_LEDB_SHIFT; } static inline u_int16_t _raw_read_CR(void); static inline u_int16_t _raw_read_CR(void){ return *(volatile u_int16_t*)(smc91_base + 0); } static inline void _raw_write_CR(u_int16_t val); static inline void _raw_write_CR(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 0) = val; } static inline u_int8_t _raw_read_CR_EPH_Power_EN(void); static inline u_int8_t _raw_read_CR_EPH_Power_EN(void){ return (_raw_read_CR() & CR_EPH_Power_EN_MASK) >> CR_EPH_Power_EN_SHIFT; } static inline u_int8_t _raw_read_CR_NO_WAIT(void); static inline u_int8_t _raw_read_CR_NO_WAIT(void){ return (_raw_read_CR() & CR_NO_WAIT_MASK) >> CR_NO_WAIT_SHIFT; } static inline u_int8_t _raw_read_CR_GPCNTRL(void); static inline u_int8_t _raw_read_CR_GPCNTRL(void){ return (_raw_read_CR() & CR_GPCNTRL_MASK) >> CR_GPCNTRL_SHIFT; } static inline u_int8_t _raw_read_CR_EXT_PHY(void); static inline u_int8_t _raw_read_CR_EXT_PHY(void){ return (_raw_read_CR() & CR_EXT_PHY_MASK) >> CR_EXT_PHY_SHIFT; } static inline u_int16_t _raw_read_BAR(void); static inline u_int16_t _raw_read_BAR(void){ return *(volatile u_int16_t*)(smc91_base + 2); } static inline void _raw_write_BAR(u_int16_t val); static inline void _raw_write_BAR(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 2) = val; } static inline u_int8_t _raw_read_BAR_A15_13(void); static inline u_int8_t _raw_read_BAR_A15_13(void){ return (_raw_read_BAR() & BAR_A15_13_MASK) >> BAR_A15_13_SHIFT; } static inline u_int8_t _raw_read_BAR_A9_5(void); static inline u_int8_t _raw_read_BAR_A9_5(void){ return (_raw_read_BAR() & BAR_A9_5_MASK) >> BAR_A9_5_SHIFT; } static inline u_int16_t _raw_read_IAR1_0(void); static inline u_int16_t _raw_read_IAR1_0(void){ return *(volatile u_int16_t*)(smc91_base + 4); } static inline void _raw_write_IAR1_0(u_int16_t val); static inline void _raw_write_IAR1_0(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 4) = val; } static inline u_int8_t _raw_read_IAR1_0_A1(void); static inline u_int8_t _raw_read_IAR1_0_A1(void){ return (_raw_read_IAR1_0() & IAR1_0_A1_MASK) >> IAR1_0_A1_SHIFT; } static inline u_int8_t _raw_read_IAR1_0_A0(void); static inline u_int8_t _raw_read_IAR1_0_A0(void){ return (_raw_read_IAR1_0() & IAR1_0_A0_MASK) >> IAR1_0_A0_SHIFT; } static inline u_int16_t _raw_read_IAR3_2(void); static inline u_int16_t _raw_read_IAR3_2(void){ return *(volatile u_int16_t*)(smc91_base + 6); } static inline void _raw_write_IAR3_2(u_int16_t val); static inline void _raw_write_IAR3_2(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 6) = val; } static inline u_int8_t _raw_read_IAR3_2_A3(void); static inline u_int8_t _raw_read_IAR3_2_A3(void){ return (_raw_read_IAR3_2() & IAR3_2_A3_MASK) >> IAR3_2_A3_SHIFT; } static inline u_int8_t _raw_read_IAR3_2_A2(void); static inline u_int8_t _raw_read_IAR3_2_A2(void){ return (_raw_read_IAR3_2() & IAR3_2_A2_MASK) >> IAR3_2_A2_SHIFT; } static inline u_int16_t _raw_read_IAR5_4(void); static inline u_int16_t _raw_read_IAR5_4(void){ return *(volatile u_int16_t*)(smc91_base + 8); } static inline void _raw_write_IAR5_4(u_int16_t val); static inline void _raw_write_IAR5_4(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 8) = val; } static inline u_int8_t _raw_read_IAR5_4_A5(void); static inline u_int8_t _raw_read_IAR5_4_A5(void){ return (_raw_read_IAR5_4() & IAR5_4_A5_MASK) >> IAR5_4_A5_SHIFT; } static inline u_int8_t _raw_read_IAR5_4_A4(void); static inline u_int8_t _raw_read_IAR5_4_A4(void){ return (_raw_read_IAR5_4() & IAR5_4_A4_MASK) >> IAR5_4_A4_SHIFT; } static inline u_int16_t _raw_read_GPR(void); static inline u_int16_t _raw_read_GPR(void){ return *(volatile u_int16_t*)(smc91_base + 10); } static inline void _raw_write_GPR(u_int16_t val); static inline void _raw_write_GPR(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 10) = val; } static inline u_int16_t _raw_read_GPR_DATA(void); static inline u_int16_t _raw_read_GPR_DATA(void){ return (_raw_read_GPR() & GPR_DATA_MASK) >> GPR_DATA_SHIFT; } static inline u_int16_t _raw_read_CTR(void); static inline u_int16_t _raw_read_CTR(void){ return *(volatile u_int16_t*)(smc91_base + 12); } static inline void _raw_write_CTR(u_int16_t val); static inline void _raw_write_CTR(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 12) = val; } static inline u_int8_t _raw_read_CTR_RCV_BAD(void); static inline u_int8_t _raw_read_CTR_RCV_BAD(void){ return (_raw_read_CTR() & CTR_RCV_BAD_MASK) >> CTR_RCV_BAD_SHIFT; } static inline u_int8_t _raw_read_CTR_AUTO_RELEASE(void); static inline u_int8_t _raw_read_CTR_AUTO_RELEASE(void){ return (_raw_read_CTR() & CTR_AUTO_RELEASE_MASK) >> CTR_AUTO_RELEASE_SHIFT; } static inline u_int8_t _raw_read_CTR_LE_ENABLE(void); static inline u_int8_t _raw_read_CTR_LE_ENABLE(void){ return (_raw_read_CTR() & CTR_LE_ENABLE_MASK) >> CTR_LE_ENABLE_SHIFT; } static inline u_int8_t _raw_read_CTR_CR_ENABLE(void); static inline u_int8_t _raw_read_CTR_CR_ENABLE(void){ return (_raw_read_CTR() & CTR_CR_ENABLE_MASK) >> CTR_CR_ENABLE_SHIFT; } static inline u_int8_t _raw_read_CTR_TE_ENABLE(void); static inline u_int8_t _raw_read_CTR_TE_ENABLE(void){ return (_raw_read_CTR() & CTR_TE_ENABLE_MASK) >> CTR_TE_ENABLE_SHIFT; } static inline u_int8_t _raw_read_CTR_EEPROM_SELECT(void); static inline u_int8_t _raw_read_CTR_EEPROM_SELECT(void){ return (_raw_read_CTR() & CTR_EEPROM_SELECT_MASK) >> CTR_EEPROM_SELECT_SHIFT; } static inline u_int8_t _raw_read_CTR_RELOAD(void); static inline u_int8_t _raw_read_CTR_RELOAD(void){ return (_raw_read_CTR() & CTR_RELOAD_MASK) >> CTR_RELOAD_SHIFT; } static inline u_int8_t _raw_read_CTR_STORE(void); static inline u_int8_t _raw_read_CTR_STORE(void){ return (_raw_read_CTR() & CTR_STORE_MASK) >> CTR_STORE_SHIFT; } static inline u_int16_t _raw_read_MMUCR(void); static inline u_int16_t _raw_read_MMUCR(void){ return *(volatile u_int16_t*)(smc91_base + 0); } static inline void _raw_write_MMUCR(u_int16_t val); static inline void _raw_write_MMUCR(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 0) = val; } static inline u_int8_t _raw_read_MMUCR_CMD(void); static inline u_int8_t _raw_read_MMUCR_CMD(void){ return (_raw_read_MMUCR() & MMUCR_CMD_MASK) >> MMUCR_CMD_SHIFT; } static inline u_int8_t _raw_read_MMUCR_BUSY(void); static inline u_int8_t _raw_read_MMUCR_BUSY(void){ return (_raw_read_MMUCR() & MMUCR_BUSY_MASK) >> MMUCR_BUSY_SHIFT; } static inline u_int16_t _raw_read_PNR(void); static inline u_int16_t _raw_read_PNR(void){ return *(volatile u_int16_t*)(smc91_base + 2); } static inline void _raw_write_PNR(u_int16_t val); static inline void _raw_write_PNR(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 2) = val; } static inline u_int8_t _raw_read_PNR_PACKET_NUMBER_AT_TX_AREA(void); static inline u_int8_t _raw_read_PNR_PACKET_NUMBER_AT_TX_AREA(void){ return (_raw_read_PNR() & PNR_PACKET_NUMBER_AT_TX_AREA_MASK) >> PNR_PACKET_NUMBER_AT_TX_AREA_SHIFT; } static inline u_int16_t _raw_read_ARR(void); static inline u_int16_t _raw_read_ARR(void){ return *(volatile u_int16_t*)(smc91_base + 2); } static inline u_int8_t _raw_read_ARR_FAILED(void); static inline u_int8_t _raw_read_ARR_FAILED(void){ return (_raw_read_ARR() & ARR_FAILED_MASK) >> ARR_FAILED_SHIFT; } static inline u_int8_t _raw_read_ARR_ALLOCATED_PACKET_NUMBER(void); static inline u_int8_t _raw_read_ARR_ALLOCATED_PACKET_NUMBER(void){ return (_raw_read_ARR() & ARR_ALLOCATED_PACKET_NUMBER_MASK) >> ARR_ALLOCATED_PACKET_NUMBER_SHIFT; } static inline u_int16_t _raw_read_FIFO(void); static inline u_int16_t _raw_read_FIFO(void){ return *(volatile u_int16_t*)(smc91_base + 4); } static inline u_int8_t _raw_read_FIFO_REMPTY(void); static inline u_int8_t _raw_read_FIFO_REMPTY(void){ return (_raw_read_FIFO() & FIFO_REMPTY_MASK) >> FIFO_REMPTY_SHIFT; } static inline u_int8_t _raw_read_FIFO_RX_FIFO_PACKET_NUMBER(void); static inline u_int8_t _raw_read_FIFO_RX_FIFO_PACKET_NUMBER(void){ return (_raw_read_FIFO() & FIFO_RX_FIFO_PACKET_NUMBER_MASK) >> FIFO_RX_FIFO_PACKET_NUMBER_SHIFT; } static inline u_int8_t _raw_read_FIFO_TEMPTY(void); static inline u_int8_t _raw_read_FIFO_TEMPTY(void){ return (_raw_read_FIFO() & FIFO_TEMPTY_MASK) >> FIFO_TEMPTY_SHIFT; } static inline u_int8_t _raw_read_FIFO_TX_FIFO_PACKET_NUMBER(void); static inline u_int8_t _raw_read_FIFO_TX_FIFO_PACKET_NUMBER(void){ return (_raw_read_FIFO() & FIFO_TX_FIFO_PACKET_NUMBER_MASK) >> FIFO_TX_FIFO_PACKET_NUMBER_SHIFT; } static inline u_int16_t _raw_read_PTR(void); static inline u_int16_t _raw_read_PTR(void){ return *(volatile u_int16_t*)(smc91_base + 6); } static inline void _raw_write_PTR(u_int16_t val); static inline void _raw_write_PTR(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 6) = val; } static inline u_int8_t _raw_read_PTR_RCV(void); static inline u_int8_t _raw_read_PTR_RCV(void){ return (_raw_read_PTR() & PTR_RCV_MASK) >> PTR_RCV_SHIFT; } static inline u_int8_t _raw_read_PTR_AUTO_INCR(void); static inline u_int8_t _raw_read_PTR_AUTO_INCR(void){ return (_raw_read_PTR() & PTR_AUTO_INCR_MASK) >> PTR_AUTO_INCR_SHIFT; } static inline u_int8_t _raw_read_PTR_READ(void); static inline u_int8_t _raw_read_PTR_READ(void){ return (_raw_read_PTR() & PTR_READ_MASK) >> PTR_READ_SHIFT; } static inline u_int8_t _raw_read_PTR_ETEN(void); static inline u_int8_t _raw_read_PTR_ETEN(void){ return (_raw_read_PTR() & PTR_ETEN_MASK) >> PTR_ETEN_SHIFT; } static inline u_int8_t _raw_read_PTR_NOT_EMPTY(void); static inline u_int8_t _raw_read_PTR_NOT_EMPTY(void){ return (_raw_read_PTR() & PTR_NOT_EMPTY_MASK) >> PTR_NOT_EMPTY_SHIFT; } static inline u_int8_t _raw_read_PTR_POINTER_HIGH(void); static inline u_int8_t _raw_read_PTR_POINTER_HIGH(void){ return (_raw_read_PTR() & PTR_POINTER_HIGH_MASK) >> PTR_POINTER_HIGH_SHIFT; } static inline u_int8_t _raw_read_PTR_POINTER_LOW(void); static inline u_int8_t _raw_read_PTR_POINTER_LOW(void){ return (_raw_read_PTR() & PTR_POINTER_LOW_MASK) >> PTR_POINTER_LOW_SHIFT; } static inline u_int16_t _raw_read_DATA(void); static inline u_int16_t _raw_read_DATA(void){ return *(volatile u_int16_t*)(smc91_base + 8); } static inline void _raw_write_DATA(u_int16_t val); static inline void _raw_write_DATA(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 8) = val; } static inline u_int16_t _raw_read_DATA_DATA(void); static inline u_int16_t _raw_read_DATA_DATA(void){ return (_raw_read_DATA() & DATA_DATA_MASK) >> DATA_DATA_SHIFT; } static inline u_int16_t _raw_read_IST(void); static inline u_int16_t _raw_read_IST(void){ return *(volatile u_int16_t*)(smc91_base + 12); } static inline u_int8_t _raw_read_IST_MDINT(void); static inline u_int8_t _raw_read_IST_MDINT(void){ return (_raw_read_IST() & IST_MDINT_MASK) >> IST_MDINT_SHIFT; } static inline u_int8_t _raw_read_IST_ERCV_INT(void); static inline u_int8_t _raw_read_IST_ERCV_INT(void){ return (_raw_read_IST() & IST_ERCV_INT_MASK) >> IST_ERCV_INT_SHIFT; } static inline u_int8_t _raw_read_IST_EPH_INT(void); static inline u_int8_t _raw_read_IST_EPH_INT(void){ return (_raw_read_IST() & IST_EPH_INT_MASK) >> IST_EPH_INT_SHIFT; } static inline u_int8_t _raw_read_IST_RX_OVRN_INT(void); static inline u_int8_t _raw_read_IST_RX_OVRN_INT(void){ return (_raw_read_IST() & IST_RX_OVRN_INT_MASK) >> IST_RX_OVRN_INT_SHIFT; } static inline u_int8_t _raw_read_IST_ALLOC_INT(void); static inline u_int8_t _raw_read_IST_ALLOC_INT(void){ return (_raw_read_IST() & IST_ALLOC_INT_MASK) >> IST_ALLOC_INT_SHIFT; } static inline u_int8_t _raw_read_IST_TX_EMPTY_INT(void); static inline u_int8_t _raw_read_IST_TX_EMPTY_INT(void){ return (_raw_read_IST() & IST_TX_EMPTY_INT_MASK) >> IST_TX_EMPTY_INT_SHIFT; } static inline u_int8_t _raw_read_IST_TX_INT(void); static inline u_int8_t _raw_read_IST_TX_INT(void){ return (_raw_read_IST() & IST_TX_INT_MASK) >> IST_TX_INT_SHIFT; } static inline u_int8_t _raw_read_IST_RCV_INT(void); static inline u_int8_t _raw_read_IST_RCV_INT(void){ return (_raw_read_IST() & IST_RCV_INT_MASK) >> IST_RCV_INT_SHIFT; } static inline void _raw_write_ACK(u_int16_t val); static inline void _raw_write_ACK(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 12) = val; } static inline u_int16_t _raw_read_MSK(void); static inline u_int16_t _raw_read_MSK(void){ return *(volatile u_int16_t*)(smc91_base + 12); } static inline void _raw_write_MSK(u_int16_t val); static inline void _raw_write_MSK(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 12) = val; } static inline u_int8_t _raw_read_MSK_MDINT(void); static inline u_int8_t _raw_read_MSK_MDINT(void){ return (_raw_read_MSK() & MSK_MDINT_MASK) >> MSK_MDINT_SHIFT; } static inline u_int8_t _raw_read_MSK_ERCV_INT(void); static inline u_int8_t _raw_read_MSK_ERCV_INT(void){ return (_raw_read_MSK() & MSK_ERCV_INT_MASK) >> MSK_ERCV_INT_SHIFT; } static inline u_int8_t _raw_read_MSK_EPH_INT(void); static inline u_int8_t _raw_read_MSK_EPH_INT(void){ return (_raw_read_MSK() & MSK_EPH_INT_MASK) >> MSK_EPH_INT_SHIFT; } static inline u_int8_t _raw_read_MSK_RX_OVRN_INT(void); static inline u_int8_t _raw_read_MSK_RX_OVRN_INT(void){ return (_raw_read_MSK() & MSK_RX_OVRN_INT_MASK) >> MSK_RX_OVRN_INT_SHIFT; } static inline u_int8_t _raw_read_MSK_ALLOC_INT(void); static inline u_int8_t _raw_read_MSK_ALLOC_INT(void){ return (_raw_read_MSK() & MSK_ALLOC_INT_MASK) >> MSK_ALLOC_INT_SHIFT; } static inline u_int8_t _raw_read_MSK_TX_EMPTY_INT(void); static inline u_int8_t _raw_read_MSK_TX_EMPTY_INT(void){ return (_raw_read_MSK() & MSK_TX_EMPTY_INT_MASK) >> MSK_TX_EMPTY_INT_SHIFT; } static inline u_int8_t _raw_read_MSK_TX_INT(void); static inline u_int8_t _raw_read_MSK_TX_INT(void){ return (_raw_read_MSK() & MSK_TX_INT_MASK) >> MSK_TX_INT_SHIFT; } static inline u_int8_t _raw_read_MSK_RCV_INT(void); static inline u_int8_t _raw_read_MSK_RCV_INT(void){ return (_raw_read_MSK() & MSK_RCV_INT_MASK) >> MSK_RCV_INT_SHIFT; } static inline u_int16_t _raw_read_MT1_0(void); static inline u_int16_t _raw_read_MT1_0(void){ return *(volatile u_int16_t*)(smc91_base + 0); } static inline void _raw_write_MT1_0(u_int16_t val); static inline void _raw_write_MT1_0(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 0) = val; } static inline u_int8_t _raw_read_MT1_0_MT1(void); static inline u_int8_t _raw_read_MT1_0_MT1(void){ return (_raw_read_MT1_0() & MT1_0_MT1_MASK) >> MT1_0_MT1_SHIFT; } static inline u_int8_t _raw_read_MT1_0_MT0(void); static inline u_int8_t _raw_read_MT1_0_MT0(void){ return (_raw_read_MT1_0() & MT1_0_MT0_MASK) >> MT1_0_MT0_SHIFT; } static inline u_int16_t _raw_read_MT3_2(void); static inline u_int16_t _raw_read_MT3_2(void){ return *(volatile u_int16_t*)(smc91_base + 2); } static inline void _raw_write_MT3_2(u_int16_t val); static inline void _raw_write_MT3_2(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 2) = val; } static inline u_int8_t _raw_read_MT3_2_MT3(void); static inline u_int8_t _raw_read_MT3_2_MT3(void){ return (_raw_read_MT3_2() & MT3_2_MT3_MASK) >> MT3_2_MT3_SHIFT; } static inline u_int8_t _raw_read_MT3_2_MT2(void); static inline u_int8_t _raw_read_MT3_2_MT2(void){ return (_raw_read_MT3_2() & MT3_2_MT2_MASK) >> MT3_2_MT2_SHIFT; } static inline u_int16_t _raw_read_MT5_4(void); static inline u_int16_t _raw_read_MT5_4(void){ return *(volatile u_int16_t*)(smc91_base + 4); } static inline void _raw_write_MT5_4(u_int16_t val); static inline void _raw_write_MT5_4(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 4) = val; } static inline u_int8_t _raw_read_MT5_4_MT5(void); static inline u_int8_t _raw_read_MT5_4_MT5(void){ return (_raw_read_MT5_4() & MT5_4_MT5_MASK) >> MT5_4_MT5_SHIFT; } static inline u_int8_t _raw_read_MT5_4_MT4(void); static inline u_int8_t _raw_read_MT5_4_MT4(void){ return (_raw_read_MT5_4() & MT5_4_MT4_MASK) >> MT5_4_MT4_SHIFT; } static inline u_int16_t _raw_read_MT7_6(void); static inline u_int16_t _raw_read_MT7_6(void){ return *(volatile u_int16_t*)(smc91_base + 6); } static inline void _raw_write_MT7_6(u_int16_t val); static inline void _raw_write_MT7_6(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 6) = val; } static inline u_int8_t _raw_read_MT7_6_MT7(void); static inline u_int8_t _raw_read_MT7_6_MT7(void){ return (_raw_read_MT7_6() & MT7_6_MT7_MASK) >> MT7_6_MT7_SHIFT; } static inline u_int8_t _raw_read_MT7_6_MT6(void); static inline u_int8_t _raw_read_MT7_6_MT6(void){ return (_raw_read_MT7_6() & MT7_6_MT6_MASK) >> MT7_6_MT6_SHIFT; } static inline u_int16_t _raw_read_MGMT(void); static inline u_int16_t _raw_read_MGMT(void){ return *(volatile u_int16_t*)(smc91_base + 8); } static inline void _raw_write_MGMT(u_int16_t val); static inline void _raw_write_MGMT(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 8) = val; } static inline u_int8_t _raw_read_MGMT_MSK_CRS100(void); static inline u_int8_t _raw_read_MGMT_MSK_CRS100(void){ return (_raw_read_MGMT() & MGMT_MSK_CRS100_MASK) >> MGMT_MSK_CRS100_SHIFT; } static inline u_int8_t _raw_read_MGMT_MDOE(void); static inline u_int8_t _raw_read_MGMT_MDOE(void){ return (_raw_read_MGMT() & MGMT_MDOE_MASK) >> MGMT_MDOE_SHIFT; } static inline u_int8_t _raw_read_MGMT_MCLK(void); static inline u_int8_t _raw_read_MGMT_MCLK(void){ return (_raw_read_MGMT() & MGMT_MCLK_MASK) >> MGMT_MCLK_SHIFT; } static inline u_int8_t _raw_read_MGMT_MDIN(void); static inline u_int8_t _raw_read_MGMT_MDIN(void){ return (_raw_read_MGMT() & MGMT_MDIN_MASK) >> MGMT_MDIN_SHIFT; } static inline u_int8_t _raw_read_MGMT_MDOUT(void); static inline u_int8_t _raw_read_MGMT_MDOUT(void){ return (_raw_read_MGMT() & MGMT_MDOUT_MASK) >> MGMT_MDOUT_SHIFT; } static inline u_int16_t _raw_read_REV(void); static inline u_int16_t _raw_read_REV(void){ return *(volatile u_int16_t*)(smc91_base + 10); } static inline u_int8_t _raw_read_REV_CHIP(void); static inline u_int8_t _raw_read_REV_CHIP(void){ return (_raw_read_REV() & REV_CHIP_MASK) >> REV_CHIP_SHIFT; } static inline u_int8_t _raw_read_REV_REV(void); static inline u_int8_t _raw_read_REV_REV(void){ return (_raw_read_REV() & REV_REV_MASK) >> REV_REV_SHIFT; } static inline u_int16_t _raw_read_ERCV(void); static inline u_int16_t _raw_read_ERCV(void){ return *(volatile u_int16_t*)(smc91_base + 12); } static inline void _raw_write_ERCV(u_int16_t val); static inline void _raw_write_ERCV(u_int16_t val){ *(volatile u_int16_t*)(smc91_base + 12) = val; } static inline u_int8_t _raw_read_ERCV_RCV_DISCRD(void); static inline u_int8_t _raw_read_ERCV_RCV_DISCRD(void){ return (_raw_read_ERCV() & ERCV_RCV_DISCRD_MASK) >> ERCV_RCV_DISCRD_SHIFT; } static inline u_int8_t _raw_read_ERCV_ERCV_THRESHOLD(void); static inline u_int8_t _raw_read_ERCV_ERCV_THRESHOLD(void){ return (_raw_read_ERCV() & ERCV_ERCV_THRESHOLD_MASK) >> ERCV_ERCV_THRESHOLD_SHIFT; } static inline u_int16_t _raw_read_Control(void); static inline u_int16_t _raw_read_Control(void){ return smc91c111_mii_get_2(0x0 + 0); } static inline void _raw_write_Control(u_int16_t val); static inline void _raw_write_Control(u_int16_t val){ smc91c111_mii_set_2(0x0 + 0, val); } static inline u_int8_t _raw_read_Control_RST(void); static inline u_int8_t _raw_read_Control_RST(void){ return (_raw_read_Control() & Control_RST_MASK) >> Control_RST_SHIFT; } static inline u_int8_t _raw_read_Control_LPBK(void); static inline u_int8_t _raw_read_Control_LPBK(void){ return (_raw_read_Control() & Control_LPBK_MASK) >> Control_LPBK_SHIFT; } static inline u_int8_t _raw_read_Control_SPEED(void); static inline u_int8_t _raw_read_Control_SPEED(void){ return (_raw_read_Control() & Control_SPEED_MASK) >> Control_SPEED_SHIFT; } static inline u_int8_t _raw_read_Control_ANEG_EN(void); static inline u_int8_t _raw_read_Control_ANEG_EN(void){ return (_raw_read_Control() & Control_ANEG_EN_MASK) >> Control_ANEG_EN_SHIFT; } static inline u_int8_t _raw_read_Control_PDN(void); static inline u_int8_t _raw_read_Control_PDN(void){ return (_raw_read_Control() & Control_PDN_MASK) >> Control_PDN_SHIFT; } static inline u_int8_t _raw_read_Control_MII_DIS(void); static inline u_int8_t _raw_read_Control_MII_DIS(void){ return (_raw_read_Control() & Control_MII_DIS_MASK) >> Control_MII_DIS_SHIFT; } static inline u_int8_t _raw_read_Control_ANEG_RST(void); static inline u_int8_t _raw_read_Control_ANEG_RST(void){ return (_raw_read_Control() & Control_ANEG_RST_MASK) >> Control_ANEG_RST_SHIFT; } static inline u_int8_t _raw_read_Control_DPLX(void); static inline u_int8_t _raw_read_Control_DPLX(void){ return (_raw_read_Control() & Control_DPLX_MASK) >> Control_DPLX_SHIFT; } static inline u_int8_t _raw_read_Control_COLST(void); static inline u_int8_t _raw_read_Control_COLST(void){ return (_raw_read_Control() & Control_COLST_MASK) >> Control_COLST_SHIFT; } static inline u_int16_t _raw_read_Status(void); static inline u_int16_t _raw_read_Status(void){ return smc91c111_mii_get_2(0x0 + 1); } static inline u_int8_t _raw_read_Status_CAP_T4(void); static inline u_int8_t _raw_read_Status_CAP_T4(void){ return (_raw_read_Status() & Status_CAP_T4_MASK) >> Status_CAP_T4_SHIFT; } static inline u_int8_t _raw_read_Status_CAP_TXF(void); static inline u_int8_t _raw_read_Status_CAP_TXF(void){ return (_raw_read_Status() & Status_CAP_TXF_MASK) >> Status_CAP_TXF_SHIFT; } static inline u_int8_t _raw_read_Status_CAP_TXH(void); static inline u_int8_t _raw_read_Status_CAP_TXH(void){ return (_raw_read_Status() & Status_CAP_TXH_MASK) >> Status_CAP_TXH_SHIFT; } static inline u_int8_t _raw_read_Status_CAP_TF(void); static inline u_int8_t _raw_read_Status_CAP_TF(void){ return (_raw_read_Status() & Status_CAP_TF_MASK) >> Status_CAP_TF_SHIFT; } static inline u_int8_t _raw_read_Status_CAP_TH(void); static inline u_int8_t _raw_read_Status_CAP_TH(void){ return (_raw_read_Status() & Status_CAP_TH_MASK) >> Status_CAP_TH_SHIFT; } static inline u_int8_t _raw_read_Status_CAP_SUPR(void); static inline u_int8_t _raw_read_Status_CAP_SUPR(void){ return (_raw_read_Status() & Status_CAP_SUPR_MASK) >> Status_CAP_SUPR_SHIFT; } static inline u_int8_t _raw_read_Status_ANEG_ACK(void); static inline u_int8_t _raw_read_Status_ANEG_ACK(void){ return (_raw_read_Status() & Status_ANEG_ACK_MASK) >> Status_ANEG_ACK_SHIFT; } static inline u_int8_t _raw_read_Status_REM_FLT(void); static inline u_int8_t _raw_read_Status_REM_FLT(void){ return (_raw_read_Status() & Status_REM_FLT_MASK) >> Status_REM_FLT_SHIFT; } static inline u_int8_t _raw_read_Status_CAP_ANEG(void); static inline u_int8_t _raw_read_Status_CAP_ANEG(void){ return (_raw_read_Status() & Status_CAP_ANEG_MASK) >> Status_CAP_ANEG_SHIFT; } static inline u_int8_t _raw_read_Status_LINK(void); static inline u_int8_t _raw_read_Status_LINK(void){ return (_raw_read_Status() & Status_LINK_MASK) >> Status_LINK_SHIFT; } static inline u_int8_t _raw_read_Status_JAB(void); static inline u_int8_t _raw_read_Status_JAB(void){ return (_raw_read_Status() & Status_JAB_MASK) >> Status_JAB_SHIFT; } static inline u_int8_t _raw_read_Status_EXREG(void); static inline u_int8_t _raw_read_Status_EXREG(void){ return (_raw_read_Status() & Status_EXREG_MASK) >> Status_EXREG_SHIFT; } static inline u_int16_t _raw_read_PHY_ID1(void); static inline u_int16_t _raw_read_PHY_ID1(void){ return smc91c111_mii_get_2(0x0 + 2); } static inline u_int16_t _raw_read_PHY_ID1_VENDOR(void); static inline u_int16_t _raw_read_PHY_ID1_VENDOR(void){ return (_raw_read_PHY_ID1() & PHY_ID1_VENDOR_MASK) >> PHY_ID1_VENDOR_SHIFT; } static inline u_int16_t _raw_read_PHY_ID2(void); static inline u_int16_t _raw_read_PHY_ID2(void){ return smc91c111_mii_get_2(0x0 + 3); } static inline u_int8_t _raw_read_PHY_ID2_OUILSB(void); static inline u_int8_t _raw_read_PHY_ID2_OUILSB(void){ return (_raw_read_PHY_ID2() & PHY_ID2_OUILSB_MASK) >> PHY_ID2_OUILSB_SHIFT; } static inline u_int8_t _raw_read_PHY_ID2_MFGR(void); static inline u_int8_t _raw_read_PHY_ID2_MFGR(void){ return (_raw_read_PHY_ID2() & PHY_ID2_MFGR_MASK) >> PHY_ID2_MFGR_SHIFT; } static inline u_int8_t _raw_read_PHY_ID2_REV(void); static inline u_int8_t _raw_read_PHY_ID2_REV(void){ return (_raw_read_PHY_ID2() & PHY_ID2_REV_MASK) >> PHY_ID2_REV_SHIFT; } static inline u_int16_t _raw_read_ANA(void); static inline u_int16_t _raw_read_ANA(void){ return smc91c111_mii_get_2(0x0 + 4); } static inline void _raw_write_ANA(u_int16_t val); static inline void _raw_write_ANA(u_int16_t val){ smc91c111_mii_set_2(0x0 + 4, val); } static inline u_int8_t _raw_read_ANA_NP(void); static inline u_int8_t _raw_read_ANA_NP(void){ return (_raw_read_ANA() & ANA_NP_MASK) >> ANA_NP_SHIFT; } static inline u_int8_t _raw_read_ANA_ACK(void); static inline u_int8_t _raw_read_ANA_ACK(void){ return (_raw_read_ANA() & ANA_ACK_MASK) >> ANA_ACK_SHIFT; } static inline u_int8_t _raw_read_ANA_RF(void); static inline u_int8_t _raw_read_ANA_RF(void){ return (_raw_read_ANA() & ANA_RF_MASK) >> ANA_RF_SHIFT; } static inline u_int8_t _raw_read_ANA_T4(void); static inline u_int8_t _raw_read_ANA_T4(void){ return (_raw_read_ANA() & ANA_T4_MASK) >> ANA_T4_SHIFT; } static inline u_int8_t _raw_read_ANA_TX_FDX(void); static inline u_int8_t _raw_read_ANA_TX_FDX(void){ return (_raw_read_ANA() & ANA_TX_FDX_MASK) >> ANA_TX_FDX_SHIFT; } static inline u_int8_t _raw_read_ANA_TX_HDX(void); static inline u_int8_t _raw_read_ANA_TX_HDX(void){ return (_raw_read_ANA() & ANA_TX_HDX_MASK) >> ANA_TX_HDX_SHIFT; } static inline u_int8_t _raw_read_ANA_TEN_FDX(void); static inline u_int8_t _raw_read_ANA_TEN_FDX(void){ return (_raw_read_ANA() & ANA_TEN_FDX_MASK) >> ANA_TEN_FDX_SHIFT; } static inline u_int8_t _raw_read_ANA_TEN_HDX(void); static inline u_int8_t _raw_read_ANA_TEN_HDX(void){ return (_raw_read_ANA() & ANA_TEN_HDX_MASK) >> ANA_TEN_HDX_SHIFT; } static inline u_int8_t _raw_read_ANA_CSMA(void); static inline u_int8_t _raw_read_ANA_CSMA(void){ return (_raw_read_ANA() & ANA_CSMA_MASK) >> ANA_CSMA_SHIFT; } static inline u_int16_t _raw_read_ANREC(void); static inline u_int16_t _raw_read_ANREC(void){ return smc91c111_mii_get_2(0x0 + 5); } static inline u_int8_t _raw_read_ANREC_NP(void); static inline u_int8_t _raw_read_ANREC_NP(void){ return (_raw_read_ANREC() & ANREC_NP_MASK) >> ANREC_NP_SHIFT; } static inline u_int8_t _raw_read_ANREC_ACK(void); static inline u_int8_t _raw_read_ANREC_ACK(void){ return (_raw_read_ANREC() & ANREC_ACK_MASK) >> ANREC_ACK_SHIFT; } static inline u_int8_t _raw_read_ANREC_RF(void); static inline u_int8_t _raw_read_ANREC_RF(void){ return (_raw_read_ANREC() & ANREC_RF_MASK) >> ANREC_RF_SHIFT; } static inline u_int8_t _raw_read_ANREC_T4(void); static inline u_int8_t _raw_read_ANREC_T4(void){ return (_raw_read_ANREC() & ANREC_T4_MASK) >> ANREC_T4_SHIFT; } static inline u_int8_t _raw_read_ANREC_TX_FDX(void); static inline u_int8_t _raw_read_ANREC_TX_FDX(void){ return (_raw_read_ANREC() & ANREC_TX_FDX_MASK) >> ANREC_TX_FDX_SHIFT; } static inline u_int8_t _raw_read_ANREC_TX_HDX(void); static inline u_int8_t _raw_read_ANREC_TX_HDX(void){ return (_raw_read_ANREC() & ANREC_TX_HDX_MASK) >> ANREC_TX_HDX_SHIFT; } static inline u_int8_t _raw_read_ANREC_TEN_FDX(void); static inline u_int8_t _raw_read_ANREC_TEN_FDX(void){ return (_raw_read_ANREC() & ANREC_TEN_FDX_MASK) >> ANREC_TEN_FDX_SHIFT; } static inline u_int8_t _raw_read_ANREC_TEN_HDX(void); static inline u_int8_t _raw_read_ANREC_TEN_HDX(void){ return (_raw_read_ANREC() & ANREC_TEN_HDX_MASK) >> ANREC_TEN_HDX_SHIFT; } static inline u_int8_t _raw_read_ANREC_CSMA(void); static inline u_int8_t _raw_read_ANREC_CSMA(void){ return (_raw_read_ANREC() & ANREC_CSMA_MASK) >> ANREC_CSMA_SHIFT; } static inline u_int16_t _raw_read_Config1(void); static inline u_int16_t _raw_read_Config1(void){ return smc91c111_mii_get_2(0x0 + 16); } static inline void _raw_write_Config1(u_int16_t val); static inline void _raw_write_Config1(u_int16_t val){ smc91c111_mii_set_2(0x0 + 16, val); } static inline u_int8_t _raw_read_Config1_LNKDIS(void); static inline u_int8_t _raw_read_Config1_LNKDIS(void){ return (_raw_read_Config1() & Config1_LNKDIS_MASK) >> Config1_LNKDIS_SHIFT; } static inline u_int8_t _raw_read_Config1_XMTDIS(void); static inline u_int8_t _raw_read_Config1_XMTDIS(void){ return (_raw_read_Config1() & Config1_XMTDIS_MASK) >> Config1_XMTDIS_SHIFT; } static inline u_int8_t _raw_read_Config1_XMTPDN(void); static inline u_int8_t _raw_read_Config1_XMTPDN(void){ return (_raw_read_Config1() & Config1_XMTPDN_MASK) >> Config1_XMTPDN_SHIFT; } static inline u_int8_t _raw_read_Config1_BYPSCR(void); static inline u_int8_t _raw_read_Config1_BYPSCR(void){ return (_raw_read_Config1() & Config1_BYPSCR_MASK) >> Config1_BYPSCR_SHIFT; } static inline u_int8_t _raw_read_Config1_UNSCDS(void); static inline u_int8_t _raw_read_Config1_UNSCDS(void){ return (_raw_read_Config1() & Config1_UNSCDS_MASK) >> Config1_UNSCDS_SHIFT; } static inline u_int8_t _raw_read_Config1_EQLZR(void); static inline u_int8_t _raw_read_Config1_EQLZR(void){ return (_raw_read_Config1() & Config1_EQLZR_MASK) >> Config1_EQLZR_SHIFT; } static inline u_int8_t _raw_read_Config1_CABLE(void); static inline u_int8_t _raw_read_Config1_CABLE(void){ return (_raw_read_Config1() & Config1_CABLE_MASK) >> Config1_CABLE_SHIFT; } static inline u_int8_t _raw_read_Config1_RLVL(void); static inline u_int8_t _raw_read_Config1_RLVL(void){ return (_raw_read_Config1() & Config1_RLVL_MASK) >> Config1_RLVL_SHIFT; } static inline u_int8_t _raw_read_Config1_TLVL(void); static inline u_int8_t _raw_read_Config1_TLVL(void){ return (_raw_read_Config1() & Config1_TLVL_MASK) >> Config1_TLVL_SHIFT; } static inline u_int8_t _raw_read_Config1_TRF(void); static inline u_int8_t _raw_read_Config1_TRF(void){ return (_raw_read_Config1() & Config1_TRF_MASK) >> Config1_TRF_SHIFT; } static inline u_int16_t _raw_read_Config2(void); static inline u_int16_t _raw_read_Config2(void){ return smc91c111_mii_get_2(0x0 + 17); } static inline void _raw_write_Config2(u_int16_t val); static inline void _raw_write_Config2(u_int16_t val){ smc91c111_mii_set_2(0x0 + 17, val); } static inline u_int8_t _raw_read_Config2_APOLDIS(void); static inline u_int8_t _raw_read_Config2_APOLDIS(void){ return (_raw_read_Config2() & Config2_APOLDIS_MASK) >> Config2_APOLDIS_SHIFT; } static inline u_int8_t _raw_read_Config2_JABDIS(void); static inline u_int8_t _raw_read_Config2_JABDIS(void){ return (_raw_read_Config2() & Config2_JABDIS_MASK) >> Config2_JABDIS_SHIFT; } static inline u_int8_t _raw_read_Config2_MREG(void); static inline u_int8_t _raw_read_Config2_MREG(void){ return (_raw_read_Config2() & Config2_MREG_MASK) >> Config2_MREG_SHIFT; } static inline u_int8_t _raw_read_Config2_INTMDIO(void); static inline u_int8_t _raw_read_Config2_INTMDIO(void){ return (_raw_read_Config2() & Config2_INTMDIO_MASK) >> Config2_INTMDIO_SHIFT; } static inline u_int16_t _raw_read_Status_Output(void); static inline u_int16_t _raw_read_Status_Output(void){ return smc91c111_mii_get_2(0x0 + 18); } static inline u_int8_t _raw_read_Status_Output_INT(void); static inline u_int8_t _raw_read_Status_Output_INT(void){ return (_raw_read_Status_Output() & Status_Output_INT_MASK) >> Status_Output_INT_SHIFT; } static inline u_int8_t _raw_read_Status_Output_LNKFAIL(void); static inline u_int8_t _raw_read_Status_Output_LNKFAIL(void){ return (_raw_read_Status_Output() & Status_Output_LNKFAIL_MASK) >> Status_Output_LNKFAIL_SHIFT; } static inline u_int8_t _raw_read_Status_Output_LOSSSYNC(void); static inline u_int8_t _raw_read_Status_Output_LOSSSYNC(void){ return (_raw_read_Status_Output() & Status_Output_LOSSSYNC_MASK) >> Status_Output_LOSSSYNC_SHIFT; } static inline u_int8_t _raw_read_Status_Output_CWRD(void); static inline u_int8_t _raw_read_Status_Output_CWRD(void){ return (_raw_read_Status_Output() & Status_Output_CWRD_MASK) >> Status_Output_CWRD_SHIFT; } static inline u_int8_t _raw_read_Status_Output_SSD(void); static inline u_int8_t _raw_read_Status_Output_SSD(void){ return (_raw_read_Status_Output() & Status_Output_SSD_MASK) >> Status_Output_SSD_SHIFT; } static inline u_int8_t _raw_read_Status_Output_ESD(void); static inline u_int8_t _raw_read_Status_Output_ESD(void){ return (_raw_read_Status_Output() & Status_Output_ESD_MASK) >> Status_Output_ESD_SHIFT; } static inline u_int8_t _raw_read_Status_Output_RPOL(void); static inline u_int8_t _raw_read_Status_Output_RPOL(void){ return (_raw_read_Status_Output() & Status_Output_RPOL_MASK) >> Status_Output_RPOL_SHIFT; } static inline u_int8_t _raw_read_Status_Output_JAB(void); static inline u_int8_t _raw_read_Status_Output_JAB(void){ return (_raw_read_Status_Output() & Status_Output_JAB_MASK) >> Status_Output_JAB_SHIFT; } static inline u_int8_t _raw_read_Status_Output_SPDDET(void); static inline u_int8_t _raw_read_Status_Output_SPDDET(void){ return (_raw_read_Status_Output() & Status_Output_SPDDET_MASK) >> Status_Output_SPDDET_SHIFT; } static inline u_int8_t _raw_read_Status_Output_DPLXDET(void); static inline u_int8_t _raw_read_Status_Output_DPLXDET(void){ return (_raw_read_Status_Output() & Status_Output_DPLXDET_MASK) >> Status_Output_DPLXDET_SHIFT; } static inline u_int16_t _raw_read_Mask(void); static inline u_int16_t _raw_read_Mask(void){ return smc91c111_mii_get_2(0x0 + 19); } static inline void _raw_write_Mask(u_int16_t val); static inline void _raw_write_Mask(u_int16_t val){ smc91c111_mii_set_2(0x0 + 19, val); } static inline u_int8_t _raw_read_Mask_MINT(void); static inline u_int8_t _raw_read_Mask_MINT(void){ return (_raw_read_Mask() & Mask_MINT_MASK) >> Mask_MINT_SHIFT; } static inline u_int8_t _raw_read_Mask_MLNKFAIL(void); static inline u_int8_t _raw_read_Mask_MLNKFAIL(void){ return (_raw_read_Mask() & Mask_MLNKFAIL_MASK) >> Mask_MLNKFAIL_SHIFT; } static inline u_int8_t _raw_read_Mask_MLOSSSYN(void); static inline u_int8_t _raw_read_Mask_MLOSSSYN(void){ return (_raw_read_Mask() & Mask_MLOSSSYN_MASK) >> Mask_MLOSSSYN_SHIFT; } static inline u_int8_t _raw_read_Mask_MCWRD(void); static inline u_int8_t _raw_read_Mask_MCWRD(void){ return (_raw_read_Mask() & Mask_MCWRD_MASK) >> Mask_MCWRD_SHIFT; } static inline u_int8_t _raw_read_Mask_MSSD(void); static inline u_int8_t _raw_read_Mask_MSSD(void){ return (_raw_read_Mask() & Mask_MSSD_MASK) >> Mask_MSSD_SHIFT; } static inline u_int8_t _raw_read_Mask_MESD(void); static inline u_int8_t _raw_read_Mask_MESD(void){ return (_raw_read_Mask() & Mask_MESD_MASK) >> Mask_MESD_SHIFT; } static inline u_int8_t _raw_read_Mask_MRPOL(void); static inline u_int8_t _raw_read_Mask_MRPOL(void){ return (_raw_read_Mask() & Mask_MRPOL_MASK) >> Mask_MRPOL_SHIFT; } static inline u_int8_t _raw_read_Mask_MJAB(void); static inline u_int8_t _raw_read_Mask_MJAB(void){ return (_raw_read_Mask() & Mask_MJAB_MASK) >> Mask_MJAB_SHIFT; } static inline u_int8_t _raw_read_Mask_MSPDDT(void); static inline u_int8_t _raw_read_Mask_MSPDDT(void){ return (_raw_read_Mask() & Mask_MSPDDT_MASK) >> Mask_MSPDDT_SHIFT; } static inline u_int8_t _raw_read_Mask_MDPLDT(void); static inline u_int8_t _raw_read_Mask_MDPLDT(void){ return (_raw_read_Mask() & Mask_MDPLDT_MASK) >> Mask_MDPLDT_SHIFT; } static inline u_int16_t _raw_read_Reserved(void); static inline u_int16_t _raw_read_Reserved(void){ return smc91c111_mii_get_2(0x0 + 20); } static inline void _raw_write_Reserved(u_int16_t val); static inline void _raw_write_Reserved(u_int16_t val){ smc91c111_mii_set_2(0x0 + 20, val); } /* accesing register BSR (read write) */ static inline u_int16_t get_BSR(void){ u_int16_t val; val = _raw_read_BSR(); return val; } static inline void set_BSR(u_int16_t val){ _raw_write_BSR(val); } static inline u_int8_t get_BSR_ID(void){ u_int16_t reg_val; reg_val = get_BSR(); return (reg_val & BSR_ID_MASK) >> BSR_ID_SHIFT; } static inline void set_BSR_ID(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_BSR(); reg_val = (reg_val & ~BSR_ID_MASK) | ((bit_val << BSR_ID_SHIFT) & BSR_ID_MASK); set_BSR(reg_val); } static inline u_int8_t mem_get_BSR_ID(u_int16_t reg_val){ return (reg_val & BSR_ID_MASK) >> BSR_ID_SHIFT; } static inline void mem_set_BSR_ID(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~BSR_ID_MASK) | ((bit_val << BSR_ID_SHIFT) & BSR_ID_MASK); } /* Warning: dont_change and volatile for register BSR bit BANK */ static inline u_int8_t get_BSR_BANK(void){ u_int16_t reg_val; reg_val = get_BSR(); return (reg_val & BSR_BANK_MASK) >> BSR_BANK_SHIFT; } static inline void set_BSR_BANK(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = (reg_val & ~BSR_BANK_MASK) | ((bit_val << BSR_BANK_SHIFT) & BSR_BANK_MASK); set_BSR(reg_val); } static inline u_int8_t mem_get_BSR_BANK(u_int16_t reg_val){ return (reg_val & BSR_BANK_MASK) >> BSR_BANK_SHIFT; } static inline void mem_set_BSR_BANK(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~BSR_BANK_MASK) | ((bit_val << BSR_BANK_SHIFT) & BSR_BANK_MASK); } /* accesing register TCR (read write) */ static inline u_int16_t get_TCR(void){ u_int16_t val; val = _raw_read_TCR(); return val; } static inline void set_TCR(u_int16_t val){ _raw_write_TCR(val); } static inline u_int8_t get_TCR_SWFDUP(void){ u_int16_t reg_val; reg_val = get_TCR(); return (reg_val & TCR_SWFDUP_MASK) >> TCR_SWFDUP_SHIFT; } static inline void set_TCR_SWFDUP(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_TCR(); reg_val = (reg_val & ~TCR_SWFDUP_MASK) | ((bit_val << TCR_SWFDUP_SHIFT) & TCR_SWFDUP_MASK); set_TCR(reg_val); } static inline u_int8_t mem_get_TCR_SWFDUP(u_int16_t reg_val){ return (reg_val & TCR_SWFDUP_MASK) >> TCR_SWFDUP_SHIFT; } static inline void mem_set_TCR_SWFDUP(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~TCR_SWFDUP_MASK) | ((bit_val << TCR_SWFDUP_SHIFT) & TCR_SWFDUP_MASK); } static inline u_int8_t get_TCR_EPH_LOOP(void){ u_int16_t reg_val; reg_val = get_TCR(); return (reg_val & TCR_EPH_LOOP_MASK) >> TCR_EPH_LOOP_SHIFT; } static inline void set_TCR_EPH_LOOP(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_TCR(); reg_val = (reg_val & ~TCR_EPH_LOOP_MASK) | ((bit_val << TCR_EPH_LOOP_SHIFT) & TCR_EPH_LOOP_MASK); set_TCR(reg_val); } static inline u_int8_t mem_get_TCR_EPH_LOOP(u_int16_t reg_val){ return (reg_val & TCR_EPH_LOOP_MASK) >> TCR_EPH_LOOP_SHIFT; } static inline void mem_set_TCR_EPH_LOOP(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~TCR_EPH_LOOP_MASK) | ((bit_val << TCR_EPH_LOOP_SHIFT) & TCR_EPH_LOOP_MASK); } static inline u_int8_t get_TCR_STP_SQET(void){ u_int16_t reg_val; reg_val = get_TCR(); return (reg_val & TCR_STP_SQET_MASK) >> TCR_STP_SQET_SHIFT; } static inline void set_TCR_STP_SQET(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_TCR(); reg_val = (reg_val & ~TCR_STP_SQET_MASK) | ((bit_val << TCR_STP_SQET_SHIFT) & TCR_STP_SQET_MASK); set_TCR(reg_val); } static inline u_int8_t mem_get_TCR_STP_SQET(u_int16_t reg_val){ return (reg_val & TCR_STP_SQET_MASK) >> TCR_STP_SQET_SHIFT; } static inline void mem_set_TCR_STP_SQET(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~TCR_STP_SQET_MASK) | ((bit_val << TCR_STP_SQET_SHIFT) & TCR_STP_SQET_MASK); } static inline u_int8_t get_TCR_FDUPLX(void){ u_int16_t reg_val; reg_val = get_TCR(); return (reg_val & TCR_FDUPLX_MASK) >> TCR_FDUPLX_SHIFT; } static inline void set_TCR_FDUPLX(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_TCR(); reg_val = (reg_val & ~TCR_FDUPLX_MASK) | ((bit_val << TCR_FDUPLX_SHIFT) & TCR_FDUPLX_MASK); set_TCR(reg_val); } static inline u_int8_t mem_get_TCR_FDUPLX(u_int16_t reg_val){ return (reg_val & TCR_FDUPLX_MASK) >> TCR_FDUPLX_SHIFT; } static inline void mem_set_TCR_FDUPLX(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~TCR_FDUPLX_MASK) | ((bit_val << TCR_FDUPLX_SHIFT) & TCR_FDUPLX_MASK); } static inline u_int8_t get_TCR_MON_CSN(void){ u_int16_t reg_val; reg_val = get_TCR(); return (reg_val & TCR_MON_CSN_MASK) >> TCR_MON_CSN_SHIFT; } static inline void set_TCR_MON_CSN(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_TCR(); reg_val = (reg_val & ~TCR_MON_CSN_MASK) | ((bit_val << TCR_MON_CSN_SHIFT) & TCR_MON_CSN_MASK); set_TCR(reg_val); } static inline u_int8_t mem_get_TCR_MON_CSN(u_int16_t reg_val){ return (reg_val & TCR_MON_CSN_MASK) >> TCR_MON_CSN_SHIFT; } static inline void mem_set_TCR_MON_CSN(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~TCR_MON_CSN_MASK) | ((bit_val << TCR_MON_CSN_SHIFT) & TCR_MON_CSN_MASK); } static inline u_int8_t get_TCR_NOCRC(void){ u_int16_t reg_val; reg_val = get_TCR(); return (reg_val & TCR_NOCRC_MASK) >> TCR_NOCRC_SHIFT; } static inline void set_TCR_NOCRC(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_TCR(); reg_val = (reg_val & ~TCR_NOCRC_MASK) | ((bit_val << TCR_NOCRC_SHIFT) & TCR_NOCRC_MASK); set_TCR(reg_val); } static inline u_int8_t mem_get_TCR_NOCRC(u_int16_t reg_val){ return (reg_val & TCR_NOCRC_MASK) >> TCR_NOCRC_SHIFT; } static inline void mem_set_TCR_NOCRC(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~TCR_NOCRC_MASK) | ((bit_val << TCR_NOCRC_SHIFT) & TCR_NOCRC_MASK); } static inline u_int8_t get_TCR_PAD_EN(void){ u_int16_t reg_val; reg_val = get_TCR(); return (reg_val & TCR_PAD_EN_MASK) >> TCR_PAD_EN_SHIFT; } static inline void set_TCR_PAD_EN(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_TCR(); reg_val = (reg_val & ~TCR_PAD_EN_MASK) | ((bit_val << TCR_PAD_EN_SHIFT) & TCR_PAD_EN_MASK); set_TCR(reg_val); } static inline u_int8_t mem_get_TCR_PAD_EN(u_int16_t reg_val){ return (reg_val & TCR_PAD_EN_MASK) >> TCR_PAD_EN_SHIFT; } static inline void mem_set_TCR_PAD_EN(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~TCR_PAD_EN_MASK) | ((bit_val << TCR_PAD_EN_SHIFT) & TCR_PAD_EN_MASK); } static inline u_int8_t get_TCR_FORCOL(void){ u_int16_t reg_val; reg_val = get_TCR(); return (reg_val & TCR_FORCOL_MASK) >> TCR_FORCOL_SHIFT; } static inline void set_TCR_FORCOL(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_TCR(); reg_val = (reg_val & ~TCR_FORCOL_MASK) | ((bit_val << TCR_FORCOL_SHIFT) & TCR_FORCOL_MASK); set_TCR(reg_val); } static inline u_int8_t mem_get_TCR_FORCOL(u_int16_t reg_val){ return (reg_val & TCR_FORCOL_MASK) >> TCR_FORCOL_SHIFT; } static inline void mem_set_TCR_FORCOL(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~TCR_FORCOL_MASK) | ((bit_val << TCR_FORCOL_SHIFT) & TCR_FORCOL_MASK); } static inline u_int8_t get_TCR_LOOP(void){ u_int16_t reg_val; reg_val = get_TCR(); return (reg_val & TCR_LOOP_MASK) >> TCR_LOOP_SHIFT; } static inline void set_TCR_LOOP(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_TCR(); reg_val = (reg_val & ~TCR_LOOP_MASK) | ((bit_val << TCR_LOOP_SHIFT) & TCR_LOOP_MASK); set_TCR(reg_val); } static inline u_int8_t mem_get_TCR_LOOP(u_int16_t reg_val){ return (reg_val & TCR_LOOP_MASK) >> TCR_LOOP_SHIFT; } static inline void mem_set_TCR_LOOP(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~TCR_LOOP_MASK) | ((bit_val << TCR_LOOP_SHIFT) & TCR_LOOP_MASK); } /* Warning: dont_change and volatile for register TCR bit TXENA */ static inline u_int8_t get_TCR_TXENA(void){ u_int16_t reg_val; reg_val = get_TCR(); return (reg_val & TCR_TXENA_MASK) >> TCR_TXENA_SHIFT; } static inline void set_TCR_TXENA(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_TCR(); reg_val = (reg_val & ~TCR_TXENA_MASK) | ((bit_val << TCR_TXENA_SHIFT) & TCR_TXENA_MASK); set_TCR(reg_val); } static inline u_int8_t mem_get_TCR_TXENA(u_int16_t reg_val){ return (reg_val & TCR_TXENA_MASK) >> TCR_TXENA_SHIFT; } static inline void mem_set_TCR_TXENA(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~TCR_TXENA_MASK) | ((bit_val << TCR_TXENA_SHIFT) & TCR_TXENA_MASK); } /* accesing register EPHSR (read only) */ static inline u_int16_t get_EPHSR(void){ u_int16_t val; val = _raw_read_EPHSR(); return val; } static inline u_int8_t get_EPHSR_TX_UNRN(void){ u_int16_t reg_val; reg_val = get_EPHSR(); return (reg_val & EPHSR_TX_UNRN_MASK) >> EPHSR_TX_UNRN_SHIFT; } static inline u_int8_t mem_get_EPHSR_TX_UNRN(u_int16_t reg_val){ return (reg_val & EPHSR_TX_UNRN_MASK) >> EPHSR_TX_UNRN_SHIFT; } static inline void mem_set_EPHSR_TX_UNRN(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~EPHSR_TX_UNRN_MASK) | ((bit_val << EPHSR_TX_UNRN_SHIFT) & EPHSR_TX_UNRN_MASK); } static inline u_int8_t get_EPHSR_LINK_OK(void){ u_int16_t reg_val; reg_val = get_EPHSR(); return (reg_val & EPHSR_LINK_OK_MASK) >> EPHSR_LINK_OK_SHIFT; } static inline u_int8_t mem_get_EPHSR_LINK_OK(u_int16_t reg_val){ return (reg_val & EPHSR_LINK_OK_MASK) >> EPHSR_LINK_OK_SHIFT; } static inline void mem_set_EPHSR_LINK_OK(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~EPHSR_LINK_OK_MASK) | ((bit_val << EPHSR_LINK_OK_SHIFT) & EPHSR_LINK_OK_MASK); } static inline u_int8_t get_EPHSR_CTR_ROL(void){ u_int16_t reg_val; reg_val = get_EPHSR(); return (reg_val & EPHSR_CTR_ROL_MASK) >> EPHSR_CTR_ROL_SHIFT; } static inline u_int8_t mem_get_EPHSR_CTR_ROL(u_int16_t reg_val){ return (reg_val & EPHSR_CTR_ROL_MASK) >> EPHSR_CTR_ROL_SHIFT; } static inline void mem_set_EPHSR_CTR_ROL(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~EPHSR_CTR_ROL_MASK) | ((bit_val << EPHSR_CTR_ROL_SHIFT) & EPHSR_CTR_ROL_MASK); } static inline u_int8_t get_EPHSR_EXC_DEF(void){ u_int16_t reg_val; reg_val = get_EPHSR(); return (reg_val & EPHSR_EXC_DEF_MASK) >> EPHSR_EXC_DEF_SHIFT; } static inline u_int8_t mem_get_EPHSR_EXC_DEF(u_int16_t reg_val){ return (reg_val & EPHSR_EXC_DEF_MASK) >> EPHSR_EXC_DEF_SHIFT; } static inline void mem_set_EPHSR_EXC_DEF(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~EPHSR_EXC_DEF_MASK) | ((bit_val << EPHSR_EXC_DEF_SHIFT) & EPHSR_EXC_DEF_MASK); } static inline u_int8_t get_EPHSR_LOST_CAR(void){ u_int16_t reg_val; reg_val = get_EPHSR(); return (reg_val & EPHSR_LOST_CAR_MASK) >> EPHSR_LOST_CAR_SHIFT; } static inline u_int8_t mem_get_EPHSR_LOST_CAR(u_int16_t reg_val){ return (reg_val & EPHSR_LOST_CAR_MASK) >> EPHSR_LOST_CAR_SHIFT; } static inline void mem_set_EPHSR_LOST_CAR(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~EPHSR_LOST_CAR_MASK) | ((bit_val << EPHSR_LOST_CAR_SHIFT) & EPHSR_LOST_CAR_MASK); } static inline u_int8_t get_EPHSR_LATCOL(void){ u_int16_t reg_val; reg_val = get_EPHSR(); return (reg_val & EPHSR_LATCOL_MASK) >> EPHSR_LATCOL_SHIFT; } static inline u_int8_t mem_get_EPHSR_LATCOL(u_int16_t reg_val){ return (reg_val & EPHSR_LATCOL_MASK) >> EPHSR_LATCOL_SHIFT; } static inline void mem_set_EPHSR_LATCOL(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~EPHSR_LATCOL_MASK) | ((bit_val << EPHSR_LATCOL_SHIFT) & EPHSR_LATCOL_MASK); } static inline u_int8_t get_EPHSR_TX_DEFR(void){ u_int16_t reg_val; reg_val = get_EPHSR(); return (reg_val & EPHSR_TX_DEFR_MASK) >> EPHSR_TX_DEFR_SHIFT; } static inline u_int8_t mem_get_EPHSR_TX_DEFR(u_int16_t reg_val){ return (reg_val & EPHSR_TX_DEFR_MASK) >> EPHSR_TX_DEFR_SHIFT; } static inline void mem_set_EPHSR_TX_DEFR(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~EPHSR_TX_DEFR_MASK) | ((bit_val << EPHSR_TX_DEFR_SHIFT) & EPHSR_TX_DEFR_MASK); } static inline u_int8_t get_EPHSR_LTX_BRD(void){ u_int16_t reg_val; reg_val = get_EPHSR(); return (reg_val & EPHSR_LTX_BRD_MASK) >> EPHSR_LTX_BRD_SHIFT; } static inline u_int8_t mem_get_EPHSR_LTX_BRD(u_int16_t reg_val){ return (reg_val & EPHSR_LTX_BRD_MASK) >> EPHSR_LTX_BRD_SHIFT; } static inline void mem_set_EPHSR_LTX_BRD(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~EPHSR_LTX_BRD_MASK) | ((bit_val << EPHSR_LTX_BRD_SHIFT) & EPHSR_LTX_BRD_MASK); } static inline u_int8_t get_EPHSR_SQET(void){ u_int16_t reg_val; reg_val = get_EPHSR(); return (reg_val & EPHSR_SQET_MASK) >> EPHSR_SQET_SHIFT; } static inline u_int8_t mem_get_EPHSR_SQET(u_int16_t reg_val){ return (reg_val & EPHSR_SQET_MASK) >> EPHSR_SQET_SHIFT; } static inline void mem_set_EPHSR_SQET(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~EPHSR_SQET_MASK) | ((bit_val << EPHSR_SQET_SHIFT) & EPHSR_SQET_MASK); } static inline u_int8_t get_EPHSR_COL16(void){ u_int16_t reg_val; reg_val = get_EPHSR(); return (reg_val & EPHSR_COL16_MASK) >> EPHSR_COL16_SHIFT; } static inline u_int8_t mem_get_EPHSR_COL16(u_int16_t reg_val){ return (reg_val & EPHSR_COL16_MASK) >> EPHSR_COL16_SHIFT; } static inline void mem_set_EPHSR_COL16(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~EPHSR_COL16_MASK) | ((bit_val << EPHSR_COL16_SHIFT) & EPHSR_COL16_MASK); } static inline u_int8_t get_EPHSR_LTX_MULT(void){ u_int16_t reg_val; reg_val = get_EPHSR(); return (reg_val & EPHSR_LTX_MULT_MASK) >> EPHSR_LTX_MULT_SHIFT; } static inline u_int8_t mem_get_EPHSR_LTX_MULT(u_int16_t reg_val){ return (reg_val & EPHSR_LTX_MULT_MASK) >> EPHSR_LTX_MULT_SHIFT; } static inline void mem_set_EPHSR_LTX_MULT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~EPHSR_LTX_MULT_MASK) | ((bit_val << EPHSR_LTX_MULT_SHIFT) & EPHSR_LTX_MULT_MASK); } static inline u_int8_t get_EPHSR_MUL_COL(void){ u_int16_t reg_val; reg_val = get_EPHSR(); return (reg_val & EPHSR_MUL_COL_MASK) >> EPHSR_MUL_COL_SHIFT; } static inline u_int8_t mem_get_EPHSR_MUL_COL(u_int16_t reg_val){ return (reg_val & EPHSR_MUL_COL_MASK) >> EPHSR_MUL_COL_SHIFT; } static inline void mem_set_EPHSR_MUL_COL(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~EPHSR_MUL_COL_MASK) | ((bit_val << EPHSR_MUL_COL_SHIFT) & EPHSR_MUL_COL_MASK); } static inline u_int8_t get_EPHSR_SNGL_COL(void){ u_int16_t reg_val; reg_val = get_EPHSR(); return (reg_val & EPHSR_SNGL_COL_MASK) >> EPHSR_SNGL_COL_SHIFT; } static inline u_int8_t mem_get_EPHSR_SNGL_COL(u_int16_t reg_val){ return (reg_val & EPHSR_SNGL_COL_MASK) >> EPHSR_SNGL_COL_SHIFT; } static inline void mem_set_EPHSR_SNGL_COL(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~EPHSR_SNGL_COL_MASK) | ((bit_val << EPHSR_SNGL_COL_SHIFT) & EPHSR_SNGL_COL_MASK); } static inline u_int8_t get_EPHSR_TX_SUC(void){ u_int16_t reg_val; reg_val = get_EPHSR(); return (reg_val & EPHSR_TX_SUC_MASK) >> EPHSR_TX_SUC_SHIFT; } static inline u_int8_t mem_get_EPHSR_TX_SUC(u_int16_t reg_val){ return (reg_val & EPHSR_TX_SUC_MASK) >> EPHSR_TX_SUC_SHIFT; } static inline void mem_set_EPHSR_TX_SUC(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~EPHSR_TX_SUC_MASK) | ((bit_val << EPHSR_TX_SUC_SHIFT) & EPHSR_TX_SUC_MASK); } /* accesing register RCR (read write) */ static inline u_int16_t get_RCR(void){ u_int16_t val; val = _raw_read_RCR(); return val; } static inline void set_RCR(u_int16_t val){ _raw_write_RCR(val); } static inline u_int8_t get_RCR_SOFT_RST(void){ u_int16_t reg_val; reg_val = get_RCR(); return (reg_val & RCR_SOFT_RST_MASK) >> RCR_SOFT_RST_SHIFT; } static inline void set_RCR_SOFT_RST(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_RCR(); reg_val = (reg_val & ~RCR_RX_ABORT_MASK) | ((0 << RCR_RX_ABORT_SHIFT) & RCR_RX_ABORT_MASK); reg_val = (reg_val & ~RCR_SOFT_RST_MASK) | ((bit_val << RCR_SOFT_RST_SHIFT) & RCR_SOFT_RST_MASK); set_RCR(reg_val); } static inline u_int8_t mem_get_RCR_SOFT_RST(u_int16_t reg_val){ return (reg_val & RCR_SOFT_RST_MASK) >> RCR_SOFT_RST_SHIFT; } static inline void mem_set_RCR_SOFT_RST(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~RCR_SOFT_RST_MASK) | ((bit_val << RCR_SOFT_RST_SHIFT) & RCR_SOFT_RST_MASK); } static inline u_int8_t get_RCR_FILT_CAR(void){ u_int16_t reg_val; reg_val = get_RCR(); return (reg_val & RCR_FILT_CAR_MASK) >> RCR_FILT_CAR_SHIFT; } static inline void set_RCR_FILT_CAR(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_RCR(); reg_val = (reg_val & ~RCR_RX_ABORT_MASK) | ((0 << RCR_RX_ABORT_SHIFT) & RCR_RX_ABORT_MASK); reg_val = (reg_val & ~RCR_FILT_CAR_MASK) | ((bit_val << RCR_FILT_CAR_SHIFT) & RCR_FILT_CAR_MASK); set_RCR(reg_val); } static inline u_int8_t mem_get_RCR_FILT_CAR(u_int16_t reg_val){ return (reg_val & RCR_FILT_CAR_MASK) >> RCR_FILT_CAR_SHIFT; } static inline void mem_set_RCR_FILT_CAR(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~RCR_FILT_CAR_MASK) | ((bit_val << RCR_FILT_CAR_SHIFT) & RCR_FILT_CAR_MASK); } static inline u_int8_t get_RCR_ABORT_ENB(void){ u_int16_t reg_val; reg_val = get_RCR(); return (reg_val & RCR_ABORT_ENB_MASK) >> RCR_ABORT_ENB_SHIFT; } static inline void set_RCR_ABORT_ENB(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_RCR(); reg_val = (reg_val & ~RCR_RX_ABORT_MASK) | ((0 << RCR_RX_ABORT_SHIFT) & RCR_RX_ABORT_MASK); reg_val = (reg_val & ~RCR_ABORT_ENB_MASK) | ((bit_val << RCR_ABORT_ENB_SHIFT) & RCR_ABORT_ENB_MASK); set_RCR(reg_val); } static inline u_int8_t mem_get_RCR_ABORT_ENB(u_int16_t reg_val){ return (reg_val & RCR_ABORT_ENB_MASK) >> RCR_ABORT_ENB_SHIFT; } static inline void mem_set_RCR_ABORT_ENB(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~RCR_ABORT_ENB_MASK) | ((bit_val << RCR_ABORT_ENB_SHIFT) & RCR_ABORT_ENB_MASK); } static inline u_int8_t get_RCR_STRIP_CRC(void){ u_int16_t reg_val; reg_val = get_RCR(); return (reg_val & RCR_STRIP_CRC_MASK) >> RCR_STRIP_CRC_SHIFT; } static inline void set_RCR_STRIP_CRC(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_RCR(); reg_val = (reg_val & ~RCR_RX_ABORT_MASK) | ((0 << RCR_RX_ABORT_SHIFT) & RCR_RX_ABORT_MASK); reg_val = (reg_val & ~RCR_STRIP_CRC_MASK) | ((bit_val << RCR_STRIP_CRC_SHIFT) & RCR_STRIP_CRC_MASK); set_RCR(reg_val); } static inline u_int8_t mem_get_RCR_STRIP_CRC(u_int16_t reg_val){ return (reg_val & RCR_STRIP_CRC_MASK) >> RCR_STRIP_CRC_SHIFT; } static inline void mem_set_RCR_STRIP_CRC(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~RCR_STRIP_CRC_MASK) | ((bit_val << RCR_STRIP_CRC_SHIFT) & RCR_STRIP_CRC_MASK); } static inline u_int8_t get_RCR_RXEN(void){ u_int16_t reg_val; reg_val = get_RCR(); return (reg_val & RCR_RXEN_MASK) >> RCR_RXEN_SHIFT; } static inline void set_RCR_RXEN(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_RCR(); reg_val = (reg_val & ~RCR_RX_ABORT_MASK) | ((0 << RCR_RX_ABORT_SHIFT) & RCR_RX_ABORT_MASK); reg_val = (reg_val & ~RCR_RXEN_MASK) | ((bit_val << RCR_RXEN_SHIFT) & RCR_RXEN_MASK); set_RCR(reg_val); } static inline u_int8_t mem_get_RCR_RXEN(u_int16_t reg_val){ return (reg_val & RCR_RXEN_MASK) >> RCR_RXEN_SHIFT; } static inline void mem_set_RCR_RXEN(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~RCR_RXEN_MASK) | ((bit_val << RCR_RXEN_SHIFT) & RCR_RXEN_MASK); } static inline u_int8_t get_RCR_ALMUL(void){ u_int16_t reg_val; reg_val = get_RCR(); return (reg_val & RCR_ALMUL_MASK) >> RCR_ALMUL_SHIFT; } static inline void set_RCR_ALMUL(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_RCR(); reg_val = (reg_val & ~RCR_RX_ABORT_MASK) | ((0 << RCR_RX_ABORT_SHIFT) & RCR_RX_ABORT_MASK); reg_val = (reg_val & ~RCR_ALMUL_MASK) | ((bit_val << RCR_ALMUL_SHIFT) & RCR_ALMUL_MASK); set_RCR(reg_val); } static inline u_int8_t mem_get_RCR_ALMUL(u_int16_t reg_val){ return (reg_val & RCR_ALMUL_MASK) >> RCR_ALMUL_SHIFT; } static inline void mem_set_RCR_ALMUL(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~RCR_ALMUL_MASK) | ((bit_val << RCR_ALMUL_SHIFT) & RCR_ALMUL_MASK); } static inline u_int8_t get_RCR_PRMS(void){ u_int16_t reg_val; reg_val = get_RCR(); return (reg_val & RCR_PRMS_MASK) >> RCR_PRMS_SHIFT; } static inline void set_RCR_PRMS(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_RCR(); reg_val = (reg_val & ~RCR_RX_ABORT_MASK) | ((0 << RCR_RX_ABORT_SHIFT) & RCR_RX_ABORT_MASK); reg_val = (reg_val & ~RCR_PRMS_MASK) | ((bit_val << RCR_PRMS_SHIFT) & RCR_PRMS_MASK); set_RCR(reg_val); } static inline u_int8_t mem_get_RCR_PRMS(u_int16_t reg_val){ return (reg_val & RCR_PRMS_MASK) >> RCR_PRMS_SHIFT; } static inline void mem_set_RCR_PRMS(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~RCR_PRMS_MASK) | ((bit_val << RCR_PRMS_SHIFT) & RCR_PRMS_MASK); } static inline u_int8_t get_RCR_RX_ABORT(void){ u_int16_t reg_val; reg_val = get_RCR(); return (reg_val & RCR_RX_ABORT_MASK) >> RCR_RX_ABORT_SHIFT; } static inline void set_RCR_RX_ABORT(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_RCR(); reg_val = (reg_val & ~RCR_RX_ABORT_MASK) | ((bit_val << RCR_RX_ABORT_SHIFT) & RCR_RX_ABORT_MASK); set_RCR(reg_val); } static inline u_int8_t mem_get_RCR_RX_ABORT(u_int16_t reg_val){ return (reg_val & RCR_RX_ABORT_MASK) >> RCR_RX_ABORT_SHIFT; } static inline void mem_set_RCR_RX_ABORT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~RCR_RX_ABORT_MASK) | ((bit_val << RCR_RX_ABORT_SHIFT) & RCR_RX_ABORT_MASK); } /* accesing register ECR (read only) */ static inline u_int16_t get_ECR(void){ u_int16_t val; val = _raw_read_ECR(); return val; } static inline u_int8_t get_ECR_EXDTX(void){ u_int16_t reg_val; reg_val = get_ECR(); return (reg_val & ECR_EXDTX_MASK) >> ECR_EXDTX_SHIFT; } static inline u_int8_t mem_get_ECR_EXDTX(u_int16_t reg_val){ return (reg_val & ECR_EXDTX_MASK) >> ECR_EXDTX_SHIFT; } static inline void mem_set_ECR_EXDTX(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ECR_EXDTX_MASK) | ((bit_val << ECR_EXDTX_SHIFT) & ECR_EXDTX_MASK); } static inline u_int8_t get_ECR_DTX(void){ u_int16_t reg_val; reg_val = get_ECR(); return (reg_val & ECR_DTX_MASK) >> ECR_DTX_SHIFT; } static inline u_int8_t mem_get_ECR_DTX(u_int16_t reg_val){ return (reg_val & ECR_DTX_MASK) >> ECR_DTX_SHIFT; } static inline void mem_set_ECR_DTX(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ECR_DTX_MASK) | ((bit_val << ECR_DTX_SHIFT) & ECR_DTX_MASK); } static inline u_int8_t get_ECR_MCOLN(void){ u_int16_t reg_val; reg_val = get_ECR(); return (reg_val & ECR_MCOLN_MASK) >> ECR_MCOLN_SHIFT; } static inline u_int8_t mem_get_ECR_MCOLN(u_int16_t reg_val){ return (reg_val & ECR_MCOLN_MASK) >> ECR_MCOLN_SHIFT; } static inline void mem_set_ECR_MCOLN(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ECR_MCOLN_MASK) | ((bit_val << ECR_MCOLN_SHIFT) & ECR_MCOLN_MASK); } static inline u_int8_t get_ECR_COLN(void){ u_int16_t reg_val; reg_val = get_ECR(); return (reg_val & ECR_COLN_MASK) >> ECR_COLN_SHIFT; } static inline u_int8_t mem_get_ECR_COLN(u_int16_t reg_val){ return (reg_val & ECR_COLN_MASK) >> ECR_COLN_SHIFT; } static inline void mem_set_ECR_COLN(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ECR_COLN_MASK) | ((bit_val << ECR_COLN_SHIFT) & ECR_COLN_MASK); } /* accesing register MIR (read only) */ static inline u_int16_t get_MIR(void){ u_int16_t val; val = _raw_read_MIR(); return val; } static inline u_int8_t get_MIR_AVAIL(void){ u_int16_t reg_val; reg_val = get_MIR(); return (reg_val & MIR_AVAIL_MASK) >> MIR_AVAIL_SHIFT; } static inline u_int8_t mem_get_MIR_AVAIL(u_int16_t reg_val){ return (reg_val & MIR_AVAIL_MASK) >> MIR_AVAIL_SHIFT; } static inline void mem_set_MIR_AVAIL(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MIR_AVAIL_MASK) | ((bit_val << MIR_AVAIL_SHIFT) & MIR_AVAIL_MASK); } static inline u_int8_t get_MIR_SIZE(void){ u_int16_t reg_val; reg_val = get_MIR(); return (reg_val & MIR_SIZE_MASK) >> MIR_SIZE_SHIFT; } static inline u_int8_t mem_get_MIR_SIZE(u_int16_t reg_val){ return (reg_val & MIR_SIZE_MASK) >> MIR_SIZE_SHIFT; } static inline void mem_set_MIR_SIZE(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MIR_SIZE_MASK) | ((bit_val << MIR_SIZE_SHIFT) & MIR_SIZE_MASK); } /* accesing register RPCR (read write) */ static inline u_int16_t get_RPCR(void){ u_int16_t val; val = _raw_read_RPCR(); return val; } static inline void set_RPCR(u_int16_t val){ _raw_write_RPCR(val); } static inline u_int8_t get_RPCR_SPEED(void){ u_int16_t reg_val; reg_val = get_RPCR(); return (reg_val & RPCR_SPEED_MASK) >> RPCR_SPEED_SHIFT; } static inline void set_RPCR_SPEED(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_RPCR(); reg_val = (reg_val & ~RPCR_SPEED_MASK) | ((bit_val << RPCR_SPEED_SHIFT) & RPCR_SPEED_MASK); set_RPCR(reg_val); } static inline u_int8_t mem_get_RPCR_SPEED(u_int16_t reg_val){ return (reg_val & RPCR_SPEED_MASK) >> RPCR_SPEED_SHIFT; } static inline void mem_set_RPCR_SPEED(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~RPCR_SPEED_MASK) | ((bit_val << RPCR_SPEED_SHIFT) & RPCR_SPEED_MASK); } static inline u_int8_t get_RPCR_DPLX(void){ u_int16_t reg_val; reg_val = get_RPCR(); return (reg_val & RPCR_DPLX_MASK) >> RPCR_DPLX_SHIFT; } static inline void set_RPCR_DPLX(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_RPCR(); reg_val = (reg_val & ~RPCR_DPLX_MASK) | ((bit_val << RPCR_DPLX_SHIFT) & RPCR_DPLX_MASK); set_RPCR(reg_val); } static inline u_int8_t mem_get_RPCR_DPLX(u_int16_t reg_val){ return (reg_val & RPCR_DPLX_MASK) >> RPCR_DPLX_SHIFT; } static inline void mem_set_RPCR_DPLX(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~RPCR_DPLX_MASK) | ((bit_val << RPCR_DPLX_SHIFT) & RPCR_DPLX_MASK); } static inline u_int8_t get_RPCR_ANEG(void){ u_int16_t reg_val; reg_val = get_RPCR(); return (reg_val & RPCR_ANEG_MASK) >> RPCR_ANEG_SHIFT; } static inline void set_RPCR_ANEG(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_RPCR(); reg_val = (reg_val & ~RPCR_ANEG_MASK) | ((bit_val << RPCR_ANEG_SHIFT) & RPCR_ANEG_MASK); set_RPCR(reg_val); } static inline u_int8_t mem_get_RPCR_ANEG(u_int16_t reg_val){ return (reg_val & RPCR_ANEG_MASK) >> RPCR_ANEG_SHIFT; } static inline void mem_set_RPCR_ANEG(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~RPCR_ANEG_MASK) | ((bit_val << RPCR_ANEG_SHIFT) & RPCR_ANEG_MASK); } static inline u_int8_t get_RPCR_LEDA(void){ u_int16_t reg_val; reg_val = get_RPCR(); return (reg_val & RPCR_LEDA_MASK) >> RPCR_LEDA_SHIFT; } static inline void set_RPCR_LEDA(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_RPCR(); reg_val = (reg_val & ~RPCR_LEDA_MASK) | ((bit_val << RPCR_LEDA_SHIFT) & RPCR_LEDA_MASK); set_RPCR(reg_val); } static inline u_int8_t mem_get_RPCR_LEDA(u_int16_t reg_val){ return (reg_val & RPCR_LEDA_MASK) >> RPCR_LEDA_SHIFT; } static inline void mem_set_RPCR_LEDA(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~RPCR_LEDA_MASK) | ((bit_val << RPCR_LEDA_SHIFT) & RPCR_LEDA_MASK); } static inline u_int8_t get_RPCR_LEDB(void){ u_int16_t reg_val; reg_val = get_RPCR(); return (reg_val & RPCR_LEDB_MASK) >> RPCR_LEDB_SHIFT; } static inline void set_RPCR_LEDB(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_RPCR(); reg_val = (reg_val & ~RPCR_LEDB_MASK) | ((bit_val << RPCR_LEDB_SHIFT) & RPCR_LEDB_MASK); set_RPCR(reg_val); } static inline u_int8_t mem_get_RPCR_LEDB(u_int16_t reg_val){ return (reg_val & RPCR_LEDB_MASK) >> RPCR_LEDB_SHIFT; } static inline void mem_set_RPCR_LEDB(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~RPCR_LEDB_MASK) | ((bit_val << RPCR_LEDB_SHIFT) & RPCR_LEDB_MASK); } /* accesing register CR (read write) */ static inline u_int16_t get_CR(void){ u_int16_t val; val = _raw_read_CR(); return val; } static inline void set_CR(u_int16_t val){ _raw_write_CR(val); } static inline u_int8_t get_CR_EPH_Power_EN(void){ u_int16_t reg_val; reg_val = get_CR(); return (reg_val & CR_EPH_Power_EN_MASK) >> CR_EPH_Power_EN_SHIFT; } static inline void set_CR_EPH_Power_EN(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_CR(); reg_val = (reg_val & ~CR_EPH_Power_EN_MASK) | ((bit_val << CR_EPH_Power_EN_SHIFT) & CR_EPH_Power_EN_MASK); set_CR(reg_val); } static inline u_int8_t mem_get_CR_EPH_Power_EN(u_int16_t reg_val){ return (reg_val & CR_EPH_Power_EN_MASK) >> CR_EPH_Power_EN_SHIFT; } static inline void mem_set_CR_EPH_Power_EN(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~CR_EPH_Power_EN_MASK) | ((bit_val << CR_EPH_Power_EN_SHIFT) & CR_EPH_Power_EN_MASK); } static inline u_int8_t get_CR_NO_WAIT(void){ u_int16_t reg_val; reg_val = get_CR(); return (reg_val & CR_NO_WAIT_MASK) >> CR_NO_WAIT_SHIFT; } static inline void set_CR_NO_WAIT(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_CR(); reg_val = (reg_val & ~CR_NO_WAIT_MASK) | ((bit_val << CR_NO_WAIT_SHIFT) & CR_NO_WAIT_MASK); set_CR(reg_val); } static inline u_int8_t mem_get_CR_NO_WAIT(u_int16_t reg_val){ return (reg_val & CR_NO_WAIT_MASK) >> CR_NO_WAIT_SHIFT; } static inline void mem_set_CR_NO_WAIT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~CR_NO_WAIT_MASK) | ((bit_val << CR_NO_WAIT_SHIFT) & CR_NO_WAIT_MASK); } static inline u_int8_t get_CR_GPCNTRL(void){ u_int16_t reg_val; reg_val = get_CR(); return (reg_val & CR_GPCNTRL_MASK) >> CR_GPCNTRL_SHIFT; } static inline void set_CR_GPCNTRL(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_CR(); reg_val = (reg_val & ~CR_GPCNTRL_MASK) | ((bit_val << CR_GPCNTRL_SHIFT) & CR_GPCNTRL_MASK); set_CR(reg_val); } static inline u_int8_t mem_get_CR_GPCNTRL(u_int16_t reg_val){ return (reg_val & CR_GPCNTRL_MASK) >> CR_GPCNTRL_SHIFT; } static inline void mem_set_CR_GPCNTRL(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~CR_GPCNTRL_MASK) | ((bit_val << CR_GPCNTRL_SHIFT) & CR_GPCNTRL_MASK); } static inline u_int8_t get_CR_EXT_PHY(void){ u_int16_t reg_val; reg_val = get_CR(); return (reg_val & CR_EXT_PHY_MASK) >> CR_EXT_PHY_SHIFT; } static inline void set_CR_EXT_PHY(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_CR(); reg_val = (reg_val & ~CR_EXT_PHY_MASK) | ((bit_val << CR_EXT_PHY_SHIFT) & CR_EXT_PHY_MASK); set_CR(reg_val); } static inline u_int8_t mem_get_CR_EXT_PHY(u_int16_t reg_val){ return (reg_val & CR_EXT_PHY_MASK) >> CR_EXT_PHY_SHIFT; } static inline void mem_set_CR_EXT_PHY(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~CR_EXT_PHY_MASK) | ((bit_val << CR_EXT_PHY_SHIFT) & CR_EXT_PHY_MASK); } /* accesing register BAR (read write) */ static inline u_int16_t get_BAR(void){ u_int16_t val; val = _raw_read_BAR(); return val; } static inline void set_BAR(u_int16_t val){ _raw_write_BAR(val); } static inline u_int8_t get_BAR_A15_13(void){ u_int16_t reg_val; reg_val = get_BAR(); return (reg_val & BAR_A15_13_MASK) >> BAR_A15_13_SHIFT; } static inline void set_BAR_A15_13(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_BAR(); reg_val = (reg_val & ~BAR_A15_13_MASK) | ((bit_val << BAR_A15_13_SHIFT) & BAR_A15_13_MASK); set_BAR(reg_val); } static inline u_int8_t mem_get_BAR_A15_13(u_int16_t reg_val){ return (reg_val & BAR_A15_13_MASK) >> BAR_A15_13_SHIFT; } static inline void mem_set_BAR_A15_13(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~BAR_A15_13_MASK) | ((bit_val << BAR_A15_13_SHIFT) & BAR_A15_13_MASK); } static inline u_int8_t get_BAR_A9_5(void){ u_int16_t reg_val; reg_val = get_BAR(); return (reg_val & BAR_A9_5_MASK) >> BAR_A9_5_SHIFT; } static inline void set_BAR_A9_5(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_BAR(); reg_val = (reg_val & ~BAR_A9_5_MASK) | ((bit_val << BAR_A9_5_SHIFT) & BAR_A9_5_MASK); set_BAR(reg_val); } static inline u_int8_t mem_get_BAR_A9_5(u_int16_t reg_val){ return (reg_val & BAR_A9_5_MASK) >> BAR_A9_5_SHIFT; } static inline void mem_set_BAR_A9_5(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~BAR_A9_5_MASK) | ((bit_val << BAR_A9_5_SHIFT) & BAR_A9_5_MASK); } /* accesing register IAR1_0 (read write) */ static inline u_int16_t get_IAR1_0(void){ u_int16_t val; val = _raw_read_IAR1_0(); return val; } static inline void set_IAR1_0(u_int16_t val){ _raw_write_IAR1_0(val); } static inline u_int8_t get_IAR1_0_A1(void){ u_int16_t reg_val; reg_val = get_IAR1_0(); return (reg_val & IAR1_0_A1_MASK) >> IAR1_0_A1_SHIFT; } static inline void set_IAR1_0_A1(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_IAR1_0(); reg_val = (reg_val & ~IAR1_0_A1_MASK) | ((bit_val << IAR1_0_A1_SHIFT) & IAR1_0_A1_MASK); set_IAR1_0(reg_val); } static inline u_int8_t mem_get_IAR1_0_A1(u_int16_t reg_val){ return (reg_val & IAR1_0_A1_MASK) >> IAR1_0_A1_SHIFT; } static inline void mem_set_IAR1_0_A1(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IAR1_0_A1_MASK) | ((bit_val << IAR1_0_A1_SHIFT) & IAR1_0_A1_MASK); } static inline u_int8_t get_IAR1_0_A0(void){ u_int16_t reg_val; reg_val = get_IAR1_0(); return (reg_val & IAR1_0_A0_MASK) >> IAR1_0_A0_SHIFT; } static inline void set_IAR1_0_A0(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_IAR1_0(); reg_val = (reg_val & ~IAR1_0_A0_MASK) | ((bit_val << IAR1_0_A0_SHIFT) & IAR1_0_A0_MASK); set_IAR1_0(reg_val); } static inline u_int8_t mem_get_IAR1_0_A0(u_int16_t reg_val){ return (reg_val & IAR1_0_A0_MASK) >> IAR1_0_A0_SHIFT; } static inline void mem_set_IAR1_0_A0(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IAR1_0_A0_MASK) | ((bit_val << IAR1_0_A0_SHIFT) & IAR1_0_A0_MASK); } /* accesing register IAR3_2 (read write) */ static inline u_int16_t get_IAR3_2(void){ u_int16_t val; val = _raw_read_IAR3_2(); return val; } static inline void set_IAR3_2(u_int16_t val){ _raw_write_IAR3_2(val); } static inline u_int8_t get_IAR3_2_A3(void){ u_int16_t reg_val; reg_val = get_IAR3_2(); return (reg_val & IAR3_2_A3_MASK) >> IAR3_2_A3_SHIFT; } static inline void set_IAR3_2_A3(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_IAR3_2(); reg_val = (reg_val & ~IAR3_2_A3_MASK) | ((bit_val << IAR3_2_A3_SHIFT) & IAR3_2_A3_MASK); set_IAR3_2(reg_val); } static inline u_int8_t mem_get_IAR3_2_A3(u_int16_t reg_val){ return (reg_val & IAR3_2_A3_MASK) >> IAR3_2_A3_SHIFT; } static inline void mem_set_IAR3_2_A3(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IAR3_2_A3_MASK) | ((bit_val << IAR3_2_A3_SHIFT) & IAR3_2_A3_MASK); } static inline u_int8_t get_IAR3_2_A2(void){ u_int16_t reg_val; reg_val = get_IAR3_2(); return (reg_val & IAR3_2_A2_MASK) >> IAR3_2_A2_SHIFT; } static inline void set_IAR3_2_A2(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_IAR3_2(); reg_val = (reg_val & ~IAR3_2_A2_MASK) | ((bit_val << IAR3_2_A2_SHIFT) & IAR3_2_A2_MASK); set_IAR3_2(reg_val); } static inline u_int8_t mem_get_IAR3_2_A2(u_int16_t reg_val){ return (reg_val & IAR3_2_A2_MASK) >> IAR3_2_A2_SHIFT; } static inline void mem_set_IAR3_2_A2(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IAR3_2_A2_MASK) | ((bit_val << IAR3_2_A2_SHIFT) & IAR3_2_A2_MASK); } /* accesing register IAR5_4 (read write) */ static inline u_int16_t get_IAR5_4(void){ u_int16_t val; val = _raw_read_IAR5_4(); return val; } static inline void set_IAR5_4(u_int16_t val){ _raw_write_IAR5_4(val); } static inline u_int8_t get_IAR5_4_A5(void){ u_int16_t reg_val; reg_val = get_IAR5_4(); return (reg_val & IAR5_4_A5_MASK) >> IAR5_4_A5_SHIFT; } static inline void set_IAR5_4_A5(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_IAR5_4(); reg_val = (reg_val & ~IAR5_4_A5_MASK) | ((bit_val << IAR5_4_A5_SHIFT) & IAR5_4_A5_MASK); set_IAR5_4(reg_val); } static inline u_int8_t mem_get_IAR5_4_A5(u_int16_t reg_val){ return (reg_val & IAR5_4_A5_MASK) >> IAR5_4_A5_SHIFT; } static inline void mem_set_IAR5_4_A5(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IAR5_4_A5_MASK) | ((bit_val << IAR5_4_A5_SHIFT) & IAR5_4_A5_MASK); } static inline u_int8_t get_IAR5_4_A4(void){ u_int16_t reg_val; reg_val = get_IAR5_4(); return (reg_val & IAR5_4_A4_MASK) >> IAR5_4_A4_SHIFT; } static inline void set_IAR5_4_A4(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_IAR5_4(); reg_val = (reg_val & ~IAR5_4_A4_MASK) | ((bit_val << IAR5_4_A4_SHIFT) & IAR5_4_A4_MASK); set_IAR5_4(reg_val); } static inline u_int8_t mem_get_IAR5_4_A4(u_int16_t reg_val){ return (reg_val & IAR5_4_A4_MASK) >> IAR5_4_A4_SHIFT; } static inline void mem_set_IAR5_4_A4(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IAR5_4_A4_MASK) | ((bit_val << IAR5_4_A4_SHIFT) & IAR5_4_A4_MASK); } /* accesing register GPR (read write) */ static inline u_int16_t get_GPR(void){ u_int16_t val; val = _raw_read_GPR(); return val; } static inline void set_GPR(u_int16_t val){ _raw_write_GPR(val); } static inline u_int16_t get_GPR_DATA(void){ u_int16_t reg_val; reg_val = get_GPR(); return (reg_val & GPR_DATA_MASK) >> GPR_DATA_SHIFT; } static inline void set_GPR_DATA(u_int16_t bit_val){ u_int16_t reg_val = 0; reg_val = (reg_val & ~GPR_DATA_MASK) | ((bit_val << GPR_DATA_SHIFT) & GPR_DATA_MASK); set_GPR(reg_val); } static inline u_int16_t mem_get_GPR_DATA(u_int16_t reg_val){ return (reg_val & GPR_DATA_MASK) >> GPR_DATA_SHIFT; } static inline void mem_set_GPR_DATA(u_int16_t *reg_val, u_int16_t bit_val){ *reg_val = (*reg_val & ~GPR_DATA_MASK) | ((bit_val << GPR_DATA_SHIFT) & GPR_DATA_MASK); } /* accesing register CTR (read write) */ static inline u_int16_t get_CTR(void){ u_int16_t val; val = _raw_read_CTR(); return val; } static inline void set_CTR(u_int16_t val){ _raw_write_CTR(val); } static inline u_int8_t get_CTR_RCV_BAD(void){ u_int16_t reg_val; reg_val = get_CTR(); return (reg_val & CTR_RCV_BAD_MASK) >> CTR_RCV_BAD_SHIFT; } static inline void set_CTR_RCV_BAD(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_CTR(); reg_val = (reg_val & ~CTR_RCV_BAD_MASK) | ((bit_val << CTR_RCV_BAD_SHIFT) & CTR_RCV_BAD_MASK); set_CTR(reg_val); } static inline u_int8_t mem_get_CTR_RCV_BAD(u_int16_t reg_val){ return (reg_val & CTR_RCV_BAD_MASK) >> CTR_RCV_BAD_SHIFT; } static inline void mem_set_CTR_RCV_BAD(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~CTR_RCV_BAD_MASK) | ((bit_val << CTR_RCV_BAD_SHIFT) & CTR_RCV_BAD_MASK); } static inline u_int8_t get_CTR_AUTO_RELEASE(void){ u_int16_t reg_val; reg_val = get_CTR(); return (reg_val & CTR_AUTO_RELEASE_MASK) >> CTR_AUTO_RELEASE_SHIFT; } static inline void set_CTR_AUTO_RELEASE(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_CTR(); reg_val = (reg_val & ~CTR_AUTO_RELEASE_MASK) | ((bit_val << CTR_AUTO_RELEASE_SHIFT) & CTR_AUTO_RELEASE_MASK); set_CTR(reg_val); } static inline u_int8_t mem_get_CTR_AUTO_RELEASE(u_int16_t reg_val){ return (reg_val & CTR_AUTO_RELEASE_MASK) >> CTR_AUTO_RELEASE_SHIFT; } static inline void mem_set_CTR_AUTO_RELEASE(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~CTR_AUTO_RELEASE_MASK) | ((bit_val << CTR_AUTO_RELEASE_SHIFT) & CTR_AUTO_RELEASE_MASK); } static inline u_int8_t get_CTR_LE_ENABLE(void){ u_int16_t reg_val; reg_val = get_CTR(); return (reg_val & CTR_LE_ENABLE_MASK) >> CTR_LE_ENABLE_SHIFT; } static inline void set_CTR_LE_ENABLE(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_CTR(); reg_val = (reg_val & ~CTR_LE_ENABLE_MASK) | ((bit_val << CTR_LE_ENABLE_SHIFT) & CTR_LE_ENABLE_MASK); set_CTR(reg_val); } static inline u_int8_t mem_get_CTR_LE_ENABLE(u_int16_t reg_val){ return (reg_val & CTR_LE_ENABLE_MASK) >> CTR_LE_ENABLE_SHIFT; } static inline void mem_set_CTR_LE_ENABLE(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~CTR_LE_ENABLE_MASK) | ((bit_val << CTR_LE_ENABLE_SHIFT) & CTR_LE_ENABLE_MASK); } static inline u_int8_t get_CTR_CR_ENABLE(void){ u_int16_t reg_val; reg_val = get_CTR(); return (reg_val & CTR_CR_ENABLE_MASK) >> CTR_CR_ENABLE_SHIFT; } static inline void set_CTR_CR_ENABLE(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_CTR(); reg_val = (reg_val & ~CTR_CR_ENABLE_MASK) | ((bit_val << CTR_CR_ENABLE_SHIFT) & CTR_CR_ENABLE_MASK); set_CTR(reg_val); } static inline u_int8_t mem_get_CTR_CR_ENABLE(u_int16_t reg_val){ return (reg_val & CTR_CR_ENABLE_MASK) >> CTR_CR_ENABLE_SHIFT; } static inline void mem_set_CTR_CR_ENABLE(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~CTR_CR_ENABLE_MASK) | ((bit_val << CTR_CR_ENABLE_SHIFT) & CTR_CR_ENABLE_MASK); } static inline u_int8_t get_CTR_TE_ENABLE(void){ u_int16_t reg_val; reg_val = get_CTR(); return (reg_val & CTR_TE_ENABLE_MASK) >> CTR_TE_ENABLE_SHIFT; } static inline void set_CTR_TE_ENABLE(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_CTR(); reg_val = (reg_val & ~CTR_TE_ENABLE_MASK) | ((bit_val << CTR_TE_ENABLE_SHIFT) & CTR_TE_ENABLE_MASK); set_CTR(reg_val); } static inline u_int8_t mem_get_CTR_TE_ENABLE(u_int16_t reg_val){ return (reg_val & CTR_TE_ENABLE_MASK) >> CTR_TE_ENABLE_SHIFT; } static inline void mem_set_CTR_TE_ENABLE(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~CTR_TE_ENABLE_MASK) | ((bit_val << CTR_TE_ENABLE_SHIFT) & CTR_TE_ENABLE_MASK); } static inline u_int8_t get_CTR_EEPROM_SELECT(void){ u_int16_t reg_val; reg_val = get_CTR(); return (reg_val & CTR_EEPROM_SELECT_MASK) >> CTR_EEPROM_SELECT_SHIFT; } static inline void set_CTR_EEPROM_SELECT(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_CTR(); reg_val = (reg_val & ~CTR_EEPROM_SELECT_MASK) | ((bit_val << CTR_EEPROM_SELECT_SHIFT) & CTR_EEPROM_SELECT_MASK); set_CTR(reg_val); } static inline u_int8_t mem_get_CTR_EEPROM_SELECT(u_int16_t reg_val){ return (reg_val & CTR_EEPROM_SELECT_MASK) >> CTR_EEPROM_SELECT_SHIFT; } static inline void mem_set_CTR_EEPROM_SELECT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~CTR_EEPROM_SELECT_MASK) | ((bit_val << CTR_EEPROM_SELECT_SHIFT) & CTR_EEPROM_SELECT_MASK); } /* Warning: dont_change and volatile for register CTR bit RELOAD */ static inline u_int8_t get_CTR_RELOAD(void){ u_int16_t reg_val; reg_val = get_CTR(); return (reg_val & CTR_RELOAD_MASK) >> CTR_RELOAD_SHIFT; } static inline void set_CTR_RELOAD(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_CTR(); reg_val = (reg_val & ~CTR_RELOAD_MASK) | ((bit_val << CTR_RELOAD_SHIFT) & CTR_RELOAD_MASK); set_CTR(reg_val); } static inline u_int8_t mem_get_CTR_RELOAD(u_int16_t reg_val){ return (reg_val & CTR_RELOAD_MASK) >> CTR_RELOAD_SHIFT; } static inline void mem_set_CTR_RELOAD(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~CTR_RELOAD_MASK) | ((bit_val << CTR_RELOAD_SHIFT) & CTR_RELOAD_MASK); } /* Warning: dont_change and volatile for register CTR bit STORE */ static inline u_int8_t get_CTR_STORE(void){ u_int16_t reg_val; reg_val = get_CTR(); return (reg_val & CTR_STORE_MASK) >> CTR_STORE_SHIFT; } static inline void set_CTR_STORE(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_CTR(); reg_val = (reg_val & ~CTR_STORE_MASK) | ((bit_val << CTR_STORE_SHIFT) & CTR_STORE_MASK); set_CTR(reg_val); } static inline u_int8_t mem_get_CTR_STORE(u_int16_t reg_val){ return (reg_val & CTR_STORE_MASK) >> CTR_STORE_SHIFT; } static inline void mem_set_CTR_STORE(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~CTR_STORE_MASK) | ((bit_val << CTR_STORE_SHIFT) & CTR_STORE_MASK); } /* accesing register MMUCR (read write) */ static inline u_int16_t get_MMUCR(void){ u_int16_t val; val = _raw_read_MMUCR(); return val; } static inline void set_MMUCR(u_int16_t val){ _raw_write_MMUCR(val); } static inline u_int8_t get_MMUCR_CMD(void){ u_int16_t reg_val; reg_val = get_MMUCR(); return (reg_val & MMUCR_CMD_MASK) >> MMUCR_CMD_SHIFT; } static inline void set_MMUCR_CMD(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = (reg_val & ~MMUCR_BUSY_MASK) | ((0 << MMUCR_BUSY_SHIFT) & MMUCR_BUSY_MASK); reg_val = (reg_val & ~MMUCR_CMD_MASK) | ((bit_val << MMUCR_CMD_SHIFT) & MMUCR_CMD_MASK); set_MMUCR(reg_val); } static inline u_int8_t mem_get_MMUCR_CMD(u_int16_t reg_val){ return (reg_val & MMUCR_CMD_MASK) >> MMUCR_CMD_SHIFT; } static inline void mem_set_MMUCR_CMD(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MMUCR_CMD_MASK) | ((bit_val << MMUCR_CMD_SHIFT) & MMUCR_CMD_MASK); } static inline u_int8_t get_MMUCR_BUSY(void){ u_int16_t reg_val; reg_val = get_MMUCR(); return (reg_val & MMUCR_BUSY_MASK) >> MMUCR_BUSY_SHIFT; } /*BUSY skipped since other bits are explicit */ static inline u_int8_t mem_get_MMUCR_BUSY(u_int16_t reg_val){ return (reg_val & MMUCR_BUSY_MASK) >> MMUCR_BUSY_SHIFT; } static inline void mem_set_MMUCR_BUSY(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MMUCR_BUSY_MASK) | ((bit_val << MMUCR_BUSY_SHIFT) & MMUCR_BUSY_MASK); } /* accesing register PNR (read write) */ static inline u_int16_t get_PNR(void){ u_int16_t val; val = _raw_read_PNR(); return val; } static inline void set_PNR(u_int16_t val){ _raw_write_PNR(val); } static inline u_int8_t get_PNR_PACKET_NUMBER_AT_TX_AREA(void){ u_int16_t reg_val; reg_val = get_PNR(); return (reg_val & PNR_PACKET_NUMBER_AT_TX_AREA_MASK) >> PNR_PACKET_NUMBER_AT_TX_AREA_SHIFT; } static inline void set_PNR_PACKET_NUMBER_AT_TX_AREA(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = (reg_val & ~PNR_PACKET_NUMBER_AT_TX_AREA_MASK) | ((bit_val << PNR_PACKET_NUMBER_AT_TX_AREA_SHIFT) & PNR_PACKET_NUMBER_AT_TX_AREA_MASK); set_PNR(reg_val); } static inline u_int8_t mem_get_PNR_PACKET_NUMBER_AT_TX_AREA(u_int16_t reg_val){ return (reg_val & PNR_PACKET_NUMBER_AT_TX_AREA_MASK) >> PNR_PACKET_NUMBER_AT_TX_AREA_SHIFT; } static inline void mem_set_PNR_PACKET_NUMBER_AT_TX_AREA(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~PNR_PACKET_NUMBER_AT_TX_AREA_MASK) | ((bit_val << PNR_PACKET_NUMBER_AT_TX_AREA_SHIFT) & PNR_PACKET_NUMBER_AT_TX_AREA_MASK); } /* accesing register ARR (read only) */ static inline u_int16_t get_ARR(void){ u_int16_t val; val = _raw_read_ARR(); return val; } static inline u_int8_t get_ARR_FAILED(void){ u_int16_t reg_val; reg_val = get_ARR(); return (reg_val & ARR_FAILED_MASK) >> ARR_FAILED_SHIFT; } static inline u_int8_t mem_get_ARR_FAILED(u_int16_t reg_val){ return (reg_val & ARR_FAILED_MASK) >> ARR_FAILED_SHIFT; } static inline void mem_set_ARR_FAILED(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ARR_FAILED_MASK) | ((bit_val << ARR_FAILED_SHIFT) & ARR_FAILED_MASK); } static inline u_int8_t get_ARR_ALLOCATED_PACKET_NUMBER(void){ u_int16_t reg_val; reg_val = get_ARR(); return (reg_val & ARR_ALLOCATED_PACKET_NUMBER_MASK) >> ARR_ALLOCATED_PACKET_NUMBER_SHIFT; } static inline u_int8_t mem_get_ARR_ALLOCATED_PACKET_NUMBER(u_int16_t reg_val){ return (reg_val & ARR_ALLOCATED_PACKET_NUMBER_MASK) >> ARR_ALLOCATED_PACKET_NUMBER_SHIFT; } static inline void mem_set_ARR_ALLOCATED_PACKET_NUMBER(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ARR_ALLOCATED_PACKET_NUMBER_MASK) | ((bit_val << ARR_ALLOCATED_PACKET_NUMBER_SHIFT) & ARR_ALLOCATED_PACKET_NUMBER_MASK); } /* accesing register FIFO (read only) */ static inline u_int16_t get_FIFO(void){ u_int16_t val; val = _raw_read_FIFO(); return val; } static inline u_int8_t get_FIFO_REMPTY(void){ u_int16_t reg_val; reg_val = get_FIFO(); return (reg_val & FIFO_REMPTY_MASK) >> FIFO_REMPTY_SHIFT; } static inline u_int8_t mem_get_FIFO_REMPTY(u_int16_t reg_val){ return (reg_val & FIFO_REMPTY_MASK) >> FIFO_REMPTY_SHIFT; } static inline void mem_set_FIFO_REMPTY(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~FIFO_REMPTY_MASK) | ((bit_val << FIFO_REMPTY_SHIFT) & FIFO_REMPTY_MASK); } static inline u_int8_t get_FIFO_RX_FIFO_PACKET_NUMBER(void){ u_int16_t reg_val; reg_val = get_FIFO(); return (reg_val & FIFO_RX_FIFO_PACKET_NUMBER_MASK) >> FIFO_RX_FIFO_PACKET_NUMBER_SHIFT; } static inline u_int8_t mem_get_FIFO_RX_FIFO_PACKET_NUMBER(u_int16_t reg_val){ return (reg_val & FIFO_RX_FIFO_PACKET_NUMBER_MASK) >> FIFO_RX_FIFO_PACKET_NUMBER_SHIFT; } static inline void mem_set_FIFO_RX_FIFO_PACKET_NUMBER(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~FIFO_RX_FIFO_PACKET_NUMBER_MASK) | ((bit_val << FIFO_RX_FIFO_PACKET_NUMBER_SHIFT) & FIFO_RX_FIFO_PACKET_NUMBER_MASK); } static inline u_int8_t get_FIFO_TEMPTY(void){ u_int16_t reg_val; reg_val = get_FIFO(); return (reg_val & FIFO_TEMPTY_MASK) >> FIFO_TEMPTY_SHIFT; } static inline u_int8_t mem_get_FIFO_TEMPTY(u_int16_t reg_val){ return (reg_val & FIFO_TEMPTY_MASK) >> FIFO_TEMPTY_SHIFT; } static inline void mem_set_FIFO_TEMPTY(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~FIFO_TEMPTY_MASK) | ((bit_val << FIFO_TEMPTY_SHIFT) & FIFO_TEMPTY_MASK); } static inline u_int8_t get_FIFO_TX_FIFO_PACKET_NUMBER(void){ u_int16_t reg_val; reg_val = get_FIFO(); return (reg_val & FIFO_TX_FIFO_PACKET_NUMBER_MASK) >> FIFO_TX_FIFO_PACKET_NUMBER_SHIFT; } static inline u_int8_t mem_get_FIFO_TX_FIFO_PACKET_NUMBER(u_int16_t reg_val){ return (reg_val & FIFO_TX_FIFO_PACKET_NUMBER_MASK) >> FIFO_TX_FIFO_PACKET_NUMBER_SHIFT; } static inline void mem_set_FIFO_TX_FIFO_PACKET_NUMBER(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~FIFO_TX_FIFO_PACKET_NUMBER_MASK) | ((bit_val << FIFO_TX_FIFO_PACKET_NUMBER_SHIFT) & FIFO_TX_FIFO_PACKET_NUMBER_MASK); } /* accesing register PTR (read write) */ static inline u_int16_t get_PTR(void){ u_int16_t val; val = _raw_read_PTR(); return val; } static inline void set_PTR(u_int16_t val){ _raw_write_PTR(val); } static inline u_int8_t get_PTR_RCV(void){ u_int16_t reg_val; reg_val = get_PTR(); return (reg_val & PTR_RCV_MASK) >> PTR_RCV_SHIFT; } /*RCV skipped since other bits are explicit */ static inline u_int8_t mem_get_PTR_RCV(u_int16_t reg_val){ return (reg_val & PTR_RCV_MASK) >> PTR_RCV_SHIFT; } static inline void mem_set_PTR_RCV(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~PTR_RCV_MASK) | ((bit_val << PTR_RCV_SHIFT) & PTR_RCV_MASK); } static inline u_int8_t get_PTR_AUTO_INCR(void){ u_int16_t reg_val; reg_val = get_PTR(); return (reg_val & PTR_AUTO_INCR_MASK) >> PTR_AUTO_INCR_SHIFT; } /*AUTO_INCR skipped since other bits are explicit */ static inline u_int8_t mem_get_PTR_AUTO_INCR(u_int16_t reg_val){ return (reg_val & PTR_AUTO_INCR_MASK) >> PTR_AUTO_INCR_SHIFT; } static inline void mem_set_PTR_AUTO_INCR(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~PTR_AUTO_INCR_MASK) | ((bit_val << PTR_AUTO_INCR_SHIFT) & PTR_AUTO_INCR_MASK); } static inline u_int8_t get_PTR_READ(void){ u_int16_t reg_val; reg_val = get_PTR(); return (reg_val & PTR_READ_MASK) >> PTR_READ_SHIFT; } /*READ skipped since other bits are explicit */ static inline u_int8_t mem_get_PTR_READ(u_int16_t reg_val){ return (reg_val & PTR_READ_MASK) >> PTR_READ_SHIFT; } static inline void mem_set_PTR_READ(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~PTR_READ_MASK) | ((bit_val << PTR_READ_SHIFT) & PTR_READ_MASK); } static inline u_int8_t get_PTR_ETEN(void){ u_int16_t reg_val; reg_val = get_PTR(); return (reg_val & PTR_ETEN_MASK) >> PTR_ETEN_SHIFT; } /*ETEN skipped since other bits are explicit */ static inline u_int8_t mem_get_PTR_ETEN(u_int16_t reg_val){ return (reg_val & PTR_ETEN_MASK) >> PTR_ETEN_SHIFT; } static inline void mem_set_PTR_ETEN(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~PTR_ETEN_MASK) | ((bit_val << PTR_ETEN_SHIFT) & PTR_ETEN_MASK); } static inline u_int8_t get_PTR_NOT_EMPTY(void){ u_int16_t reg_val; reg_val = get_PTR(); return (reg_val & PTR_NOT_EMPTY_MASK) >> PTR_NOT_EMPTY_SHIFT; } /*NOT_EMPTY skipped since other bits are explicit */ static inline u_int8_t mem_get_PTR_NOT_EMPTY(u_int16_t reg_val){ return (reg_val & PTR_NOT_EMPTY_MASK) >> PTR_NOT_EMPTY_SHIFT; } static inline void mem_set_PTR_NOT_EMPTY(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~PTR_NOT_EMPTY_MASK) | ((bit_val << PTR_NOT_EMPTY_SHIFT) & PTR_NOT_EMPTY_MASK); } static inline u_int8_t get_PTR_POINTER_HIGH(void){ u_int16_t reg_val; reg_val = get_PTR(); return (reg_val & PTR_POINTER_HIGH_MASK) >> PTR_POINTER_HIGH_SHIFT; } /*POINTER_HIGH skipped since other bits are explicit */ static inline u_int8_t mem_get_PTR_POINTER_HIGH(u_int16_t reg_val){ return (reg_val & PTR_POINTER_HIGH_MASK) >> PTR_POINTER_HIGH_SHIFT; } static inline void mem_set_PTR_POINTER_HIGH(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~PTR_POINTER_HIGH_MASK) | ((bit_val << PTR_POINTER_HIGH_SHIFT) & PTR_POINTER_HIGH_MASK); } static inline u_int8_t get_PTR_POINTER_LOW(void){ u_int16_t reg_val; reg_val = get_PTR(); return (reg_val & PTR_POINTER_LOW_MASK) >> PTR_POINTER_LOW_SHIFT; } /*POINTER_LOW skipped since other bits are explicit */ static inline u_int8_t mem_get_PTR_POINTER_LOW(u_int16_t reg_val){ return (reg_val & PTR_POINTER_LOW_MASK) >> PTR_POINTER_LOW_SHIFT; } static inline void mem_set_PTR_POINTER_LOW(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~PTR_POINTER_LOW_MASK) | ((bit_val << PTR_POINTER_LOW_SHIFT) & PTR_POINTER_LOW_MASK); } /* accesing register DATA (read write) */ static inline u_int16_t get_DATA(void){ u_int16_t val; val = _raw_read_DATA(); return val; } static inline void set_DATA(u_int16_t val){ _raw_write_DATA(val); } static inline u_int16_t get_DATA_DATA(void){ u_int16_t reg_val; reg_val = get_DATA(); return (reg_val & DATA_DATA_MASK) >> DATA_DATA_SHIFT; } static inline void set_DATA_DATA(u_int16_t bit_val){ u_int16_t reg_val = 0; reg_val = (reg_val & ~DATA_DATA_MASK) | ((bit_val << DATA_DATA_SHIFT) & DATA_DATA_MASK); set_DATA(reg_val); } static inline u_int16_t mem_get_DATA_DATA(u_int16_t reg_val){ return (reg_val & DATA_DATA_MASK) >> DATA_DATA_SHIFT; } static inline void mem_set_DATA_DATA(u_int16_t *reg_val, u_int16_t bit_val){ *reg_val = (*reg_val & ~DATA_DATA_MASK) | ((bit_val << DATA_DATA_SHIFT) & DATA_DATA_MASK); } /* accesing register IST (read only) */ static inline u_int16_t get_IST(void){ u_int16_t val; val = _raw_read_IST(); return val; } static inline u_int8_t get_IST_MDINT(void){ u_int16_t reg_val; reg_val = get_IST(); return (reg_val & IST_MDINT_MASK) >> IST_MDINT_SHIFT; } static inline u_int8_t mem_get_IST_MDINT(u_int16_t reg_val){ return (reg_val & IST_MDINT_MASK) >> IST_MDINT_SHIFT; } static inline void mem_set_IST_MDINT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IST_MDINT_MASK) | ((bit_val << IST_MDINT_SHIFT) & IST_MDINT_MASK); } static inline u_int8_t get_IST_ERCV_INT(void){ u_int16_t reg_val; reg_val = get_IST(); return (reg_val & IST_ERCV_INT_MASK) >> IST_ERCV_INT_SHIFT; } static inline u_int8_t mem_get_IST_ERCV_INT(u_int16_t reg_val){ return (reg_val & IST_ERCV_INT_MASK) >> IST_ERCV_INT_SHIFT; } static inline void mem_set_IST_ERCV_INT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IST_ERCV_INT_MASK) | ((bit_val << IST_ERCV_INT_SHIFT) & IST_ERCV_INT_MASK); } static inline u_int8_t get_IST_EPH_INT(void){ u_int16_t reg_val; reg_val = get_IST(); return (reg_val & IST_EPH_INT_MASK) >> IST_EPH_INT_SHIFT; } static inline u_int8_t mem_get_IST_EPH_INT(u_int16_t reg_val){ return (reg_val & IST_EPH_INT_MASK) >> IST_EPH_INT_SHIFT; } static inline void mem_set_IST_EPH_INT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IST_EPH_INT_MASK) | ((bit_val << IST_EPH_INT_SHIFT) & IST_EPH_INT_MASK); } static inline u_int8_t get_IST_RX_OVRN_INT(void){ u_int16_t reg_val; reg_val = get_IST(); return (reg_val & IST_RX_OVRN_INT_MASK) >> IST_RX_OVRN_INT_SHIFT; } static inline u_int8_t mem_get_IST_RX_OVRN_INT(u_int16_t reg_val){ return (reg_val & IST_RX_OVRN_INT_MASK) >> IST_RX_OVRN_INT_SHIFT; } static inline void mem_set_IST_RX_OVRN_INT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IST_RX_OVRN_INT_MASK) | ((bit_val << IST_RX_OVRN_INT_SHIFT) & IST_RX_OVRN_INT_MASK); } static inline u_int8_t get_IST_ALLOC_INT(void){ u_int16_t reg_val; reg_val = get_IST(); return (reg_val & IST_ALLOC_INT_MASK) >> IST_ALLOC_INT_SHIFT; } static inline u_int8_t mem_get_IST_ALLOC_INT(u_int16_t reg_val){ return (reg_val & IST_ALLOC_INT_MASK) >> IST_ALLOC_INT_SHIFT; } static inline void mem_set_IST_ALLOC_INT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IST_ALLOC_INT_MASK) | ((bit_val << IST_ALLOC_INT_SHIFT) & IST_ALLOC_INT_MASK); } static inline u_int8_t get_IST_TX_EMPTY_INT(void){ u_int16_t reg_val; reg_val = get_IST(); return (reg_val & IST_TX_EMPTY_INT_MASK) >> IST_TX_EMPTY_INT_SHIFT; } static inline u_int8_t mem_get_IST_TX_EMPTY_INT(u_int16_t reg_val){ return (reg_val & IST_TX_EMPTY_INT_MASK) >> IST_TX_EMPTY_INT_SHIFT; } static inline void mem_set_IST_TX_EMPTY_INT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IST_TX_EMPTY_INT_MASK) | ((bit_val << IST_TX_EMPTY_INT_SHIFT) & IST_TX_EMPTY_INT_MASK); } static inline u_int8_t get_IST_TX_INT(void){ u_int16_t reg_val; reg_val = get_IST(); return (reg_val & IST_TX_INT_MASK) >> IST_TX_INT_SHIFT; } static inline u_int8_t mem_get_IST_TX_INT(u_int16_t reg_val){ return (reg_val & IST_TX_INT_MASK) >> IST_TX_INT_SHIFT; } static inline void mem_set_IST_TX_INT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IST_TX_INT_MASK) | ((bit_val << IST_TX_INT_SHIFT) & IST_TX_INT_MASK); } static inline u_int8_t get_IST_RCV_INT(void){ u_int16_t reg_val; reg_val = get_IST(); return (reg_val & IST_RCV_INT_MASK) >> IST_RCV_INT_SHIFT; } static inline u_int8_t mem_get_IST_RCV_INT(u_int16_t reg_val){ return (reg_val & IST_RCV_INT_MASK) >> IST_RCV_INT_SHIFT; } static inline void mem_set_IST_RCV_INT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~IST_RCV_INT_MASK) | ((bit_val << IST_RCV_INT_SHIFT) & IST_RCV_INT_MASK); } /* accesing register ACK (write only) */ static inline void set_ACK(u_int16_t val){ _raw_write_ACK(val); } /*MDINT skipped since other bits are explicit */ static inline u_int8_t mem_get_ACK_MDINT(u_int16_t reg_val){ return (reg_val & ACK_MDINT_MASK) >> ACK_MDINT_SHIFT; } static inline void mem_set_ACK_MDINT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ACK_MDINT_MASK) | ((bit_val << ACK_MDINT_SHIFT) & ACK_MDINT_MASK); } /*ERCV_INT skipped since other bits are explicit */ static inline u_int8_t mem_get_ACK_ERCV_INT(u_int16_t reg_val){ return (reg_val & ACK_ERCV_INT_MASK) >> ACK_ERCV_INT_SHIFT; } static inline void mem_set_ACK_ERCV_INT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ACK_ERCV_INT_MASK) | ((bit_val << ACK_ERCV_INT_SHIFT) & ACK_ERCV_INT_MASK); } /*RX_OVRN_INT skipped since other bits are explicit */ static inline u_int8_t mem_get_ACK_RX_OVRN_INT(u_int16_t reg_val){ return (reg_val & ACK_RX_OVRN_INT_MASK) >> ACK_RX_OVRN_INT_SHIFT; } static inline void mem_set_ACK_RX_OVRN_INT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ACK_RX_OVRN_INT_MASK) | ((bit_val << ACK_RX_OVRN_INT_SHIFT) & ACK_RX_OVRN_INT_MASK); } /*TX_EMPTY_INT skipped since other bits are explicit */ static inline u_int8_t mem_get_ACK_TX_EMPTY_INT(u_int16_t reg_val){ return (reg_val & ACK_TX_EMPTY_INT_MASK) >> ACK_TX_EMPTY_INT_SHIFT; } static inline void mem_set_ACK_TX_EMPTY_INT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ACK_TX_EMPTY_INT_MASK) | ((bit_val << ACK_TX_EMPTY_INT_SHIFT) & ACK_TX_EMPTY_INT_MASK); } /*TX_INT skipped since other bits are explicit */ static inline u_int8_t mem_get_ACK_TX_INT(u_int16_t reg_val){ return (reg_val & ACK_TX_INT_MASK) >> ACK_TX_INT_SHIFT; } static inline void mem_set_ACK_TX_INT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ACK_TX_INT_MASK) | ((bit_val << ACK_TX_INT_SHIFT) & ACK_TX_INT_MASK); } /* accesing register MSK (read write) */ static inline u_int16_t get_MSK(void){ u_int16_t val; val = _raw_read_MSK(); return val; } static inline void set_MSK(u_int16_t val){ _raw_write_MSK(val); } static inline u_int8_t get_MSK_MDINT(void){ u_int16_t reg_val; reg_val = get_MSK(); return (reg_val & MSK_MDINT_MASK) >> MSK_MDINT_SHIFT; } static inline void set_MSK_MDINT(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_MSK(); reg_val = (reg_val & ~MSK_RSV_0_7_MASK) | ((0 << MSK_RSV_0_7_SHIFT) & MSK_RSV_0_7_MASK); reg_val = (reg_val & ~MSK_MDINT_MASK) | ((bit_val << MSK_MDINT_SHIFT) & MSK_MDINT_MASK); set_MSK(reg_val); } static inline u_int8_t mem_get_MSK_MDINT(u_int16_t reg_val){ return (reg_val & MSK_MDINT_MASK) >> MSK_MDINT_SHIFT; } static inline void mem_set_MSK_MDINT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MSK_MDINT_MASK) | ((bit_val << MSK_MDINT_SHIFT) & MSK_MDINT_MASK); } static inline u_int8_t get_MSK_ERCV_INT(void){ u_int16_t reg_val; reg_val = get_MSK(); return (reg_val & MSK_ERCV_INT_MASK) >> MSK_ERCV_INT_SHIFT; } static inline void set_MSK_ERCV_INT(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_MSK(); reg_val = (reg_val & ~MSK_RSV_0_7_MASK) | ((0 << MSK_RSV_0_7_SHIFT) & MSK_RSV_0_7_MASK); reg_val = (reg_val & ~MSK_ERCV_INT_MASK) | ((bit_val << MSK_ERCV_INT_SHIFT) & MSK_ERCV_INT_MASK); set_MSK(reg_val); } static inline u_int8_t mem_get_MSK_ERCV_INT(u_int16_t reg_val){ return (reg_val & MSK_ERCV_INT_MASK) >> MSK_ERCV_INT_SHIFT; } static inline void mem_set_MSK_ERCV_INT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MSK_ERCV_INT_MASK) | ((bit_val << MSK_ERCV_INT_SHIFT) & MSK_ERCV_INT_MASK); } static inline u_int8_t get_MSK_EPH_INT(void){ u_int16_t reg_val; reg_val = get_MSK(); return (reg_val & MSK_EPH_INT_MASK) >> MSK_EPH_INT_SHIFT; } static inline void set_MSK_EPH_INT(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_MSK(); reg_val = (reg_val & ~MSK_RSV_0_7_MASK) | ((0 << MSK_RSV_0_7_SHIFT) & MSK_RSV_0_7_MASK); reg_val = (reg_val & ~MSK_EPH_INT_MASK) | ((bit_val << MSK_EPH_INT_SHIFT) & MSK_EPH_INT_MASK); set_MSK(reg_val); } static inline u_int8_t mem_get_MSK_EPH_INT(u_int16_t reg_val){ return (reg_val & MSK_EPH_INT_MASK) >> MSK_EPH_INT_SHIFT; } static inline void mem_set_MSK_EPH_INT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MSK_EPH_INT_MASK) | ((bit_val << MSK_EPH_INT_SHIFT) & MSK_EPH_INT_MASK); } static inline u_int8_t get_MSK_RX_OVRN_INT(void){ u_int16_t reg_val; reg_val = get_MSK(); return (reg_val & MSK_RX_OVRN_INT_MASK) >> MSK_RX_OVRN_INT_SHIFT; } static inline void set_MSK_RX_OVRN_INT(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_MSK(); reg_val = (reg_val & ~MSK_RSV_0_7_MASK) | ((0 << MSK_RSV_0_7_SHIFT) & MSK_RSV_0_7_MASK); reg_val = (reg_val & ~MSK_RX_OVRN_INT_MASK) | ((bit_val << MSK_RX_OVRN_INT_SHIFT) & MSK_RX_OVRN_INT_MASK); set_MSK(reg_val); } static inline u_int8_t mem_get_MSK_RX_OVRN_INT(u_int16_t reg_val){ return (reg_val & MSK_RX_OVRN_INT_MASK) >> MSK_RX_OVRN_INT_SHIFT; } static inline void mem_set_MSK_RX_OVRN_INT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MSK_RX_OVRN_INT_MASK) | ((bit_val << MSK_RX_OVRN_INT_SHIFT) & MSK_RX_OVRN_INT_MASK); } static inline u_int8_t get_MSK_ALLOC_INT(void){ u_int16_t reg_val; reg_val = get_MSK(); return (reg_val & MSK_ALLOC_INT_MASK) >> MSK_ALLOC_INT_SHIFT; } static inline void set_MSK_ALLOC_INT(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_MSK(); reg_val = (reg_val & ~MSK_RSV_0_7_MASK) | ((0 << MSK_RSV_0_7_SHIFT) & MSK_RSV_0_7_MASK); reg_val = (reg_val & ~MSK_ALLOC_INT_MASK) | ((bit_val << MSK_ALLOC_INT_SHIFT) & MSK_ALLOC_INT_MASK); set_MSK(reg_val); } static inline u_int8_t mem_get_MSK_ALLOC_INT(u_int16_t reg_val){ return (reg_val & MSK_ALLOC_INT_MASK) >> MSK_ALLOC_INT_SHIFT; } static inline void mem_set_MSK_ALLOC_INT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MSK_ALLOC_INT_MASK) | ((bit_val << MSK_ALLOC_INT_SHIFT) & MSK_ALLOC_INT_MASK); } static inline u_int8_t get_MSK_TX_EMPTY_INT(void){ u_int16_t reg_val; reg_val = get_MSK(); return (reg_val & MSK_TX_EMPTY_INT_MASK) >> MSK_TX_EMPTY_INT_SHIFT; } static inline void set_MSK_TX_EMPTY_INT(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_MSK(); reg_val = (reg_val & ~MSK_RSV_0_7_MASK) | ((0 << MSK_RSV_0_7_SHIFT) & MSK_RSV_0_7_MASK); reg_val = (reg_val & ~MSK_TX_EMPTY_INT_MASK) | ((bit_val << MSK_TX_EMPTY_INT_SHIFT) & MSK_TX_EMPTY_INT_MASK); set_MSK(reg_val); } static inline u_int8_t mem_get_MSK_TX_EMPTY_INT(u_int16_t reg_val){ return (reg_val & MSK_TX_EMPTY_INT_MASK) >> MSK_TX_EMPTY_INT_SHIFT; } static inline void mem_set_MSK_TX_EMPTY_INT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MSK_TX_EMPTY_INT_MASK) | ((bit_val << MSK_TX_EMPTY_INT_SHIFT) & MSK_TX_EMPTY_INT_MASK); } static inline u_int8_t get_MSK_TX_INT(void){ u_int16_t reg_val; reg_val = get_MSK(); return (reg_val & MSK_TX_INT_MASK) >> MSK_TX_INT_SHIFT; } static inline void set_MSK_TX_INT(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_MSK(); reg_val = (reg_val & ~MSK_RSV_0_7_MASK) | ((0 << MSK_RSV_0_7_SHIFT) & MSK_RSV_0_7_MASK); reg_val = (reg_val & ~MSK_TX_INT_MASK) | ((bit_val << MSK_TX_INT_SHIFT) & MSK_TX_INT_MASK); set_MSK(reg_val); } static inline u_int8_t mem_get_MSK_TX_INT(u_int16_t reg_val){ return (reg_val & MSK_TX_INT_MASK) >> MSK_TX_INT_SHIFT; } static inline void mem_set_MSK_TX_INT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MSK_TX_INT_MASK) | ((bit_val << MSK_TX_INT_SHIFT) & MSK_TX_INT_MASK); } static inline u_int8_t get_MSK_RCV_INT(void){ u_int16_t reg_val; reg_val = get_MSK(); return (reg_val & MSK_RCV_INT_MASK) >> MSK_RCV_INT_SHIFT; } static inline void set_MSK_RCV_INT(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_MSK(); reg_val = (reg_val & ~MSK_RSV_0_7_MASK) | ((0 << MSK_RSV_0_7_SHIFT) & MSK_RSV_0_7_MASK); reg_val = (reg_val & ~MSK_RCV_INT_MASK) | ((bit_val << MSK_RCV_INT_SHIFT) & MSK_RCV_INT_MASK); set_MSK(reg_val); } static inline u_int8_t mem_get_MSK_RCV_INT(u_int16_t reg_val){ return (reg_val & MSK_RCV_INT_MASK) >> MSK_RCV_INT_SHIFT; } static inline void mem_set_MSK_RCV_INT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MSK_RCV_INT_MASK) | ((bit_val << MSK_RCV_INT_SHIFT) & MSK_RCV_INT_MASK); } /* accesing register MT1_0 (read write) */ static inline u_int16_t get_MT1_0(void){ u_int16_t val; val = _raw_read_MT1_0(); return val; } static inline void set_MT1_0(u_int16_t val){ _raw_write_MT1_0(val); } static inline u_int8_t get_MT1_0_MT1(void){ u_int16_t reg_val; reg_val = get_MT1_0(); return (reg_val & MT1_0_MT1_MASK) >> MT1_0_MT1_SHIFT; } static inline void set_MT1_0_MT1(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_MT1_0(); reg_val = (reg_val & ~MT1_0_MT1_MASK) | ((bit_val << MT1_0_MT1_SHIFT) & MT1_0_MT1_MASK); set_MT1_0(reg_val); } static inline u_int8_t mem_get_MT1_0_MT1(u_int16_t reg_val){ return (reg_val & MT1_0_MT1_MASK) >> MT1_0_MT1_SHIFT; } static inline void mem_set_MT1_0_MT1(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MT1_0_MT1_MASK) | ((bit_val << MT1_0_MT1_SHIFT) & MT1_0_MT1_MASK); } static inline u_int8_t get_MT1_0_MT0(void){ u_int16_t reg_val; reg_val = get_MT1_0(); return (reg_val & MT1_0_MT0_MASK) >> MT1_0_MT0_SHIFT; } static inline void set_MT1_0_MT0(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_MT1_0(); reg_val = (reg_val & ~MT1_0_MT0_MASK) | ((bit_val << MT1_0_MT0_SHIFT) & MT1_0_MT0_MASK); set_MT1_0(reg_val); } static inline u_int8_t mem_get_MT1_0_MT0(u_int16_t reg_val){ return (reg_val & MT1_0_MT0_MASK) >> MT1_0_MT0_SHIFT; } static inline void mem_set_MT1_0_MT0(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MT1_0_MT0_MASK) | ((bit_val << MT1_0_MT0_SHIFT) & MT1_0_MT0_MASK); } /* accesing register MT3_2 (read write) */ static inline u_int16_t get_MT3_2(void){ u_int16_t val; val = _raw_read_MT3_2(); return val; } static inline void set_MT3_2(u_int16_t val){ _raw_write_MT3_2(val); } static inline u_int8_t get_MT3_2_MT3(void){ u_int16_t reg_val; reg_val = get_MT3_2(); return (reg_val & MT3_2_MT3_MASK) >> MT3_2_MT3_SHIFT; } static inline void set_MT3_2_MT3(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_MT3_2(); reg_val = (reg_val & ~MT3_2_MT3_MASK) | ((bit_val << MT3_2_MT3_SHIFT) & MT3_2_MT3_MASK); set_MT3_2(reg_val); } static inline u_int8_t mem_get_MT3_2_MT3(u_int16_t reg_val){ return (reg_val & MT3_2_MT3_MASK) >> MT3_2_MT3_SHIFT; } static inline void mem_set_MT3_2_MT3(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MT3_2_MT3_MASK) | ((bit_val << MT3_2_MT3_SHIFT) & MT3_2_MT3_MASK); } static inline u_int8_t get_MT3_2_MT2(void){ u_int16_t reg_val; reg_val = get_MT3_2(); return (reg_val & MT3_2_MT2_MASK) >> MT3_2_MT2_SHIFT; } static inline void set_MT3_2_MT2(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_MT3_2(); reg_val = (reg_val & ~MT3_2_MT2_MASK) | ((bit_val << MT3_2_MT2_SHIFT) & MT3_2_MT2_MASK); set_MT3_2(reg_val); } static inline u_int8_t mem_get_MT3_2_MT2(u_int16_t reg_val){ return (reg_val & MT3_2_MT2_MASK) >> MT3_2_MT2_SHIFT; } static inline void mem_set_MT3_2_MT2(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MT3_2_MT2_MASK) | ((bit_val << MT3_2_MT2_SHIFT) & MT3_2_MT2_MASK); } /* accesing register MT5_4 (read write) */ static inline u_int16_t get_MT5_4(void){ u_int16_t val; val = _raw_read_MT5_4(); return val; } static inline void set_MT5_4(u_int16_t val){ _raw_write_MT5_4(val); } static inline u_int8_t get_MT5_4_MT5(void){ u_int16_t reg_val; reg_val = get_MT5_4(); return (reg_val & MT5_4_MT5_MASK) >> MT5_4_MT5_SHIFT; } static inline void set_MT5_4_MT5(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_MT5_4(); reg_val = (reg_val & ~MT5_4_MT5_MASK) | ((bit_val << MT5_4_MT5_SHIFT) & MT5_4_MT5_MASK); set_MT5_4(reg_val); } static inline u_int8_t mem_get_MT5_4_MT5(u_int16_t reg_val){ return (reg_val & MT5_4_MT5_MASK) >> MT5_4_MT5_SHIFT; } static inline void mem_set_MT5_4_MT5(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MT5_4_MT5_MASK) | ((bit_val << MT5_4_MT5_SHIFT) & MT5_4_MT5_MASK); } static inline u_int8_t get_MT5_4_MT4(void){ u_int16_t reg_val; reg_val = get_MT5_4(); return (reg_val & MT5_4_MT4_MASK) >> MT5_4_MT4_SHIFT; } static inline void set_MT5_4_MT4(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_MT5_4(); reg_val = (reg_val & ~MT5_4_MT4_MASK) | ((bit_val << MT5_4_MT4_SHIFT) & MT5_4_MT4_MASK); set_MT5_4(reg_val); } static inline u_int8_t mem_get_MT5_4_MT4(u_int16_t reg_val){ return (reg_val & MT5_4_MT4_MASK) >> MT5_4_MT4_SHIFT; } static inline void mem_set_MT5_4_MT4(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MT5_4_MT4_MASK) | ((bit_val << MT5_4_MT4_SHIFT) & MT5_4_MT4_MASK); } /* accesing register MT7_6 (read write) */ static inline u_int16_t get_MT7_6(void){ u_int16_t val; val = _raw_read_MT7_6(); return val; } static inline void set_MT7_6(u_int16_t val){ _raw_write_MT7_6(val); } static inline u_int8_t get_MT7_6_MT7(void){ u_int16_t reg_val; reg_val = get_MT7_6(); return (reg_val & MT7_6_MT7_MASK) >> MT7_6_MT7_SHIFT; } static inline void set_MT7_6_MT7(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_MT7_6(); reg_val = (reg_val & ~MT7_6_MT7_MASK) | ((bit_val << MT7_6_MT7_SHIFT) & MT7_6_MT7_MASK); set_MT7_6(reg_val); } static inline u_int8_t mem_get_MT7_6_MT7(u_int16_t reg_val){ return (reg_val & MT7_6_MT7_MASK) >> MT7_6_MT7_SHIFT; } static inline void mem_set_MT7_6_MT7(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MT7_6_MT7_MASK) | ((bit_val << MT7_6_MT7_SHIFT) & MT7_6_MT7_MASK); } static inline u_int8_t get_MT7_6_MT6(void){ u_int16_t reg_val; reg_val = get_MT7_6(); return (reg_val & MT7_6_MT6_MASK) >> MT7_6_MT6_SHIFT; } static inline void set_MT7_6_MT6(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_MT7_6(); reg_val = (reg_val & ~MT7_6_MT6_MASK) | ((bit_val << MT7_6_MT6_SHIFT) & MT7_6_MT6_MASK); set_MT7_6(reg_val); } static inline u_int8_t mem_get_MT7_6_MT6(u_int16_t reg_val){ return (reg_val & MT7_6_MT6_MASK) >> MT7_6_MT6_SHIFT; } static inline void mem_set_MT7_6_MT6(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MT7_6_MT6_MASK) | ((bit_val << MT7_6_MT6_SHIFT) & MT7_6_MT6_MASK); } /* accesing register MGMT (read write) */ static inline u_int16_t get_MGMT(void){ u_int16_t val; val = _raw_read_MGMT(); return val; } static inline void set_MGMT(u_int16_t val){ _raw_write_MGMT(val); } static inline u_int8_t get_MGMT_MSK_CRS100(void){ u_int16_t reg_val; reg_val = get_MGMT(); return (reg_val & MGMT_MSK_CRS100_MASK) >> MGMT_MSK_CRS100_SHIFT; } /*MSK_CRS100 skipped since other bits are explicit */ static inline u_int8_t mem_get_MGMT_MSK_CRS100(u_int16_t reg_val){ return (reg_val & MGMT_MSK_CRS100_MASK) >> MGMT_MSK_CRS100_SHIFT; } static inline void mem_set_MGMT_MSK_CRS100(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MGMT_MSK_CRS100_MASK) | ((bit_val << MGMT_MSK_CRS100_SHIFT) & MGMT_MSK_CRS100_MASK); } static inline u_int8_t get_MGMT_MDOE(void){ u_int16_t reg_val; reg_val = get_MGMT(); return (reg_val & MGMT_MDOE_MASK) >> MGMT_MDOE_SHIFT; } /*MDOE skipped since other bits are explicit */ static inline u_int8_t mem_get_MGMT_MDOE(u_int16_t reg_val){ return (reg_val & MGMT_MDOE_MASK) >> MGMT_MDOE_SHIFT; } static inline void mem_set_MGMT_MDOE(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MGMT_MDOE_MASK) | ((bit_val << MGMT_MDOE_SHIFT) & MGMT_MDOE_MASK); } static inline u_int8_t get_MGMT_MCLK(void){ u_int16_t reg_val; reg_val = get_MGMT(); return (reg_val & MGMT_MCLK_MASK) >> MGMT_MCLK_SHIFT; } /*MCLK skipped since other bits are explicit */ static inline u_int8_t mem_get_MGMT_MCLK(u_int16_t reg_val){ return (reg_val & MGMT_MCLK_MASK) >> MGMT_MCLK_SHIFT; } static inline void mem_set_MGMT_MCLK(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MGMT_MCLK_MASK) | ((bit_val << MGMT_MCLK_SHIFT) & MGMT_MCLK_MASK); } static inline u_int8_t get_MGMT_MDIN(void){ u_int16_t reg_val; reg_val = get_MGMT(); return (reg_val & MGMT_MDIN_MASK) >> MGMT_MDIN_SHIFT; } /*MDIN skipped since other bits are explicit */ static inline u_int8_t mem_get_MGMT_MDIN(u_int16_t reg_val){ return (reg_val & MGMT_MDIN_MASK) >> MGMT_MDIN_SHIFT; } static inline void mem_set_MGMT_MDIN(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MGMT_MDIN_MASK) | ((bit_val << MGMT_MDIN_SHIFT) & MGMT_MDIN_MASK); } static inline u_int8_t get_MGMT_MDOUT(void){ u_int16_t reg_val; reg_val = get_MGMT(); return (reg_val & MGMT_MDOUT_MASK) >> MGMT_MDOUT_SHIFT; } /*MDOUT skipped since other bits are explicit */ static inline u_int8_t mem_get_MGMT_MDOUT(u_int16_t reg_val){ return (reg_val & MGMT_MDOUT_MASK) >> MGMT_MDOUT_SHIFT; } static inline void mem_set_MGMT_MDOUT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~MGMT_MDOUT_MASK) | ((bit_val << MGMT_MDOUT_SHIFT) & MGMT_MDOUT_MASK); } /* accesing register REV (read only) */ static inline u_int16_t get_REV(void){ u_int16_t val; val = _raw_read_REV(); return val; } static inline u_int8_t get_REV_CHIP(void){ u_int16_t reg_val; reg_val = get_REV(); return (reg_val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; } static inline u_int8_t mem_get_REV_CHIP(u_int16_t reg_val){ return (reg_val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; } static inline void mem_set_REV_CHIP(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~REV_CHIP_MASK) | ((bit_val << REV_CHIP_SHIFT) & REV_CHIP_MASK); } static inline u_int8_t get_REV_REV(void){ u_int16_t reg_val; reg_val = get_REV(); return (reg_val & REV_REV_MASK) >> REV_REV_SHIFT; } static inline u_int8_t mem_get_REV_REV(u_int16_t reg_val){ return (reg_val & REV_REV_MASK) >> REV_REV_SHIFT; } static inline void mem_set_REV_REV(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~REV_REV_MASK) | ((bit_val << REV_REV_SHIFT) & REV_REV_MASK); } /* accesing register ERCV (read write) */ static inline u_int16_t get_ERCV(void){ u_int16_t val; val = _raw_read_ERCV(); return val; } static inline void set_ERCV(u_int16_t val){ _raw_write_ERCV(val); } static inline u_int8_t get_ERCV_RCV_DISCRD(void){ u_int16_t reg_val; reg_val = get_ERCV(); return (reg_val & ERCV_RCV_DISCRD_MASK) >> ERCV_RCV_DISCRD_SHIFT; } /*RCV_DISCRD skipped since other bits are explicit */ static inline u_int8_t mem_get_ERCV_RCV_DISCRD(u_int16_t reg_val){ return (reg_val & ERCV_RCV_DISCRD_MASK) >> ERCV_RCV_DISCRD_SHIFT; } static inline void mem_set_ERCV_RCV_DISCRD(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ERCV_RCV_DISCRD_MASK) | ((bit_val << ERCV_RCV_DISCRD_SHIFT) & ERCV_RCV_DISCRD_MASK); } static inline u_int8_t get_ERCV_ERCV_THRESHOLD(void){ u_int16_t reg_val; reg_val = get_ERCV(); return (reg_val & ERCV_ERCV_THRESHOLD_MASK) >> ERCV_ERCV_THRESHOLD_SHIFT; } /*ERCV_THRESHOLD skipped since other bits are explicit */ static inline u_int8_t mem_get_ERCV_ERCV_THRESHOLD(u_int16_t reg_val){ return (reg_val & ERCV_ERCV_THRESHOLD_MASK) >> ERCV_ERCV_THRESHOLD_SHIFT; } static inline void mem_set_ERCV_ERCV_THRESHOLD(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ERCV_ERCV_THRESHOLD_MASK) | ((bit_val << ERCV_ERCV_THRESHOLD_SHIFT) & ERCV_ERCV_THRESHOLD_MASK); } /* accesing register Control (read write) */ static inline u_int16_t get_Control(void){ u_int16_t val; val = _raw_read_Control(); return val; } static inline void set_Control(u_int16_t val){ _raw_write_Control(val); } /* Warning: dont_change and volatile for register Control bit RST */ static inline u_int8_t get_Control_RST(void){ u_int16_t reg_val; reg_val = get_Control(); return (reg_val & Control_RST_MASK) >> Control_RST_SHIFT; } static inline void set_Control_RST(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Control(); reg_val = (reg_val & ~Control_RSV_0_6_MASK) | ((0 << Control_RSV_0_6_SHIFT) & Control_RSV_0_6_MASK); reg_val = (reg_val & ~Control_RST_MASK) | ((bit_val << Control_RST_SHIFT) & Control_RST_MASK); set_Control(reg_val); } static inline u_int8_t mem_get_Control_RST(u_int16_t reg_val){ return (reg_val & Control_RST_MASK) >> Control_RST_SHIFT; } static inline void mem_set_Control_RST(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Control_RST_MASK) | ((bit_val << Control_RST_SHIFT) & Control_RST_MASK); } static inline u_int8_t get_Control_LPBK(void){ u_int16_t reg_val; reg_val = get_Control(); return (reg_val & Control_LPBK_MASK) >> Control_LPBK_SHIFT; } static inline void set_Control_LPBK(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Control(); reg_val = (reg_val & ~Control_RSV_0_6_MASK) | ((0 << Control_RSV_0_6_SHIFT) & Control_RSV_0_6_MASK); reg_val = (reg_val & ~Control_LPBK_MASK) | ((bit_val << Control_LPBK_SHIFT) & Control_LPBK_MASK); set_Control(reg_val); } static inline u_int8_t mem_get_Control_LPBK(u_int16_t reg_val){ return (reg_val & Control_LPBK_MASK) >> Control_LPBK_SHIFT; } static inline void mem_set_Control_LPBK(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Control_LPBK_MASK) | ((bit_val << Control_LPBK_SHIFT) & Control_LPBK_MASK); } static inline u_int8_t get_Control_SPEED(void){ u_int16_t reg_val; reg_val = get_Control(); return (reg_val & Control_SPEED_MASK) >> Control_SPEED_SHIFT; } static inline void set_Control_SPEED(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Control(); reg_val = (reg_val & ~Control_RSV_0_6_MASK) | ((0 << Control_RSV_0_6_SHIFT) & Control_RSV_0_6_MASK); reg_val = (reg_val & ~Control_SPEED_MASK) | ((bit_val << Control_SPEED_SHIFT) & Control_SPEED_MASK); set_Control(reg_val); } static inline u_int8_t mem_get_Control_SPEED(u_int16_t reg_val){ return (reg_val & Control_SPEED_MASK) >> Control_SPEED_SHIFT; } static inline void mem_set_Control_SPEED(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Control_SPEED_MASK) | ((bit_val << Control_SPEED_SHIFT) & Control_SPEED_MASK); } static inline u_int8_t get_Control_ANEG_EN(void){ u_int16_t reg_val; reg_val = get_Control(); return (reg_val & Control_ANEG_EN_MASK) >> Control_ANEG_EN_SHIFT; } static inline void set_Control_ANEG_EN(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Control(); reg_val = (reg_val & ~Control_RSV_0_6_MASK) | ((0 << Control_RSV_0_6_SHIFT) & Control_RSV_0_6_MASK); reg_val = (reg_val & ~Control_ANEG_EN_MASK) | ((bit_val << Control_ANEG_EN_SHIFT) & Control_ANEG_EN_MASK); set_Control(reg_val); } static inline u_int8_t mem_get_Control_ANEG_EN(u_int16_t reg_val){ return (reg_val & Control_ANEG_EN_MASK) >> Control_ANEG_EN_SHIFT; } static inline void mem_set_Control_ANEG_EN(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Control_ANEG_EN_MASK) | ((bit_val << Control_ANEG_EN_SHIFT) & Control_ANEG_EN_MASK); } static inline u_int8_t get_Control_PDN(void){ u_int16_t reg_val; reg_val = get_Control(); return (reg_val & Control_PDN_MASK) >> Control_PDN_SHIFT; } static inline void set_Control_PDN(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Control(); reg_val = (reg_val & ~Control_RSV_0_6_MASK) | ((0 << Control_RSV_0_6_SHIFT) & Control_RSV_0_6_MASK); reg_val = (reg_val & ~Control_PDN_MASK) | ((bit_val << Control_PDN_SHIFT) & Control_PDN_MASK); set_Control(reg_val); } static inline u_int8_t mem_get_Control_PDN(u_int16_t reg_val){ return (reg_val & Control_PDN_MASK) >> Control_PDN_SHIFT; } static inline void mem_set_Control_PDN(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Control_PDN_MASK) | ((bit_val << Control_PDN_SHIFT) & Control_PDN_MASK); } static inline u_int8_t get_Control_MII_DIS(void){ u_int16_t reg_val; reg_val = get_Control(); return (reg_val & Control_MII_DIS_MASK) >> Control_MII_DIS_SHIFT; } static inline void set_Control_MII_DIS(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Control(); reg_val = (reg_val & ~Control_RSV_0_6_MASK) | ((0 << Control_RSV_0_6_SHIFT) & Control_RSV_0_6_MASK); reg_val = (reg_val & ~Control_MII_DIS_MASK) | ((bit_val << Control_MII_DIS_SHIFT) & Control_MII_DIS_MASK); set_Control(reg_val); } static inline u_int8_t mem_get_Control_MII_DIS(u_int16_t reg_val){ return (reg_val & Control_MII_DIS_MASK) >> Control_MII_DIS_SHIFT; } static inline void mem_set_Control_MII_DIS(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Control_MII_DIS_MASK) | ((bit_val << Control_MII_DIS_SHIFT) & Control_MII_DIS_MASK); } /* Warning: dont_change and volatile for register Control bit ANEG_RST */ static inline u_int8_t get_Control_ANEG_RST(void){ u_int16_t reg_val; reg_val = get_Control(); return (reg_val & Control_ANEG_RST_MASK) >> Control_ANEG_RST_SHIFT; } static inline void set_Control_ANEG_RST(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Control(); reg_val = (reg_val & ~Control_RSV_0_6_MASK) | ((0 << Control_RSV_0_6_SHIFT) & Control_RSV_0_6_MASK); reg_val = (reg_val & ~Control_ANEG_RST_MASK) | ((bit_val << Control_ANEG_RST_SHIFT) & Control_ANEG_RST_MASK); set_Control(reg_val); } static inline u_int8_t mem_get_Control_ANEG_RST(u_int16_t reg_val){ return (reg_val & Control_ANEG_RST_MASK) >> Control_ANEG_RST_SHIFT; } static inline void mem_set_Control_ANEG_RST(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Control_ANEG_RST_MASK) | ((bit_val << Control_ANEG_RST_SHIFT) & Control_ANEG_RST_MASK); } static inline u_int8_t get_Control_DPLX(void){ u_int16_t reg_val; reg_val = get_Control(); return (reg_val & Control_DPLX_MASK) >> Control_DPLX_SHIFT; } static inline void set_Control_DPLX(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Control(); reg_val = (reg_val & ~Control_RSV_0_6_MASK) | ((0 << Control_RSV_0_6_SHIFT) & Control_RSV_0_6_MASK); reg_val = (reg_val & ~Control_DPLX_MASK) | ((bit_val << Control_DPLX_SHIFT) & Control_DPLX_MASK); set_Control(reg_val); } static inline u_int8_t mem_get_Control_DPLX(u_int16_t reg_val){ return (reg_val & Control_DPLX_MASK) >> Control_DPLX_SHIFT; } static inline void mem_set_Control_DPLX(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Control_DPLX_MASK) | ((bit_val << Control_DPLX_SHIFT) & Control_DPLX_MASK); } static inline u_int8_t get_Control_COLST(void){ u_int16_t reg_val; reg_val = get_Control(); return (reg_val & Control_COLST_MASK) >> Control_COLST_SHIFT; } static inline void set_Control_COLST(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Control(); reg_val = (reg_val & ~Control_RSV_0_6_MASK) | ((0 << Control_RSV_0_6_SHIFT) & Control_RSV_0_6_MASK); reg_val = (reg_val & ~Control_COLST_MASK) | ((bit_val << Control_COLST_SHIFT) & Control_COLST_MASK); set_Control(reg_val); } static inline u_int8_t mem_get_Control_COLST(u_int16_t reg_val){ return (reg_val & Control_COLST_MASK) >> Control_COLST_SHIFT; } static inline void mem_set_Control_COLST(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Control_COLST_MASK) | ((bit_val << Control_COLST_SHIFT) & Control_COLST_MASK); } /* accesing register Status (read only) */ static inline u_int16_t get_Status(void){ u_int16_t val; val = _raw_read_Status(); return val; } static inline u_int8_t get_Status_CAP_T4(void){ u_int16_t reg_val; reg_val = get_Status(); return (reg_val & Status_CAP_T4_MASK) >> Status_CAP_T4_SHIFT; } static inline u_int8_t mem_get_Status_CAP_T4(u_int16_t reg_val){ return (reg_val & Status_CAP_T4_MASK) >> Status_CAP_T4_SHIFT; } static inline void mem_set_Status_CAP_T4(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_CAP_T4_MASK) | ((bit_val << Status_CAP_T4_SHIFT) & Status_CAP_T4_MASK); } static inline u_int8_t get_Status_CAP_TXF(void){ u_int16_t reg_val; reg_val = get_Status(); return (reg_val & Status_CAP_TXF_MASK) >> Status_CAP_TXF_SHIFT; } static inline u_int8_t mem_get_Status_CAP_TXF(u_int16_t reg_val){ return (reg_val & Status_CAP_TXF_MASK) >> Status_CAP_TXF_SHIFT; } static inline void mem_set_Status_CAP_TXF(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_CAP_TXF_MASK) | ((bit_val << Status_CAP_TXF_SHIFT) & Status_CAP_TXF_MASK); } static inline u_int8_t get_Status_CAP_TXH(void){ u_int16_t reg_val; reg_val = get_Status(); return (reg_val & Status_CAP_TXH_MASK) >> Status_CAP_TXH_SHIFT; } static inline u_int8_t mem_get_Status_CAP_TXH(u_int16_t reg_val){ return (reg_val & Status_CAP_TXH_MASK) >> Status_CAP_TXH_SHIFT; } static inline void mem_set_Status_CAP_TXH(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_CAP_TXH_MASK) | ((bit_val << Status_CAP_TXH_SHIFT) & Status_CAP_TXH_MASK); } static inline u_int8_t get_Status_CAP_TF(void){ u_int16_t reg_val; reg_val = get_Status(); return (reg_val & Status_CAP_TF_MASK) >> Status_CAP_TF_SHIFT; } static inline u_int8_t mem_get_Status_CAP_TF(u_int16_t reg_val){ return (reg_val & Status_CAP_TF_MASK) >> Status_CAP_TF_SHIFT; } static inline void mem_set_Status_CAP_TF(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_CAP_TF_MASK) | ((bit_val << Status_CAP_TF_SHIFT) & Status_CAP_TF_MASK); } static inline u_int8_t get_Status_CAP_TH(void){ u_int16_t reg_val; reg_val = get_Status(); return (reg_val & Status_CAP_TH_MASK) >> Status_CAP_TH_SHIFT; } static inline u_int8_t mem_get_Status_CAP_TH(u_int16_t reg_val){ return (reg_val & Status_CAP_TH_MASK) >> Status_CAP_TH_SHIFT; } static inline void mem_set_Status_CAP_TH(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_CAP_TH_MASK) | ((bit_val << Status_CAP_TH_SHIFT) & Status_CAP_TH_MASK); } static inline u_int8_t get_Status_CAP_SUPR(void){ u_int16_t reg_val; reg_val = get_Status(); return (reg_val & Status_CAP_SUPR_MASK) >> Status_CAP_SUPR_SHIFT; } static inline u_int8_t mem_get_Status_CAP_SUPR(u_int16_t reg_val){ return (reg_val & Status_CAP_SUPR_MASK) >> Status_CAP_SUPR_SHIFT; } static inline void mem_set_Status_CAP_SUPR(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_CAP_SUPR_MASK) | ((bit_val << Status_CAP_SUPR_SHIFT) & Status_CAP_SUPR_MASK); } static inline u_int8_t get_Status_ANEG_ACK(void){ u_int16_t reg_val; reg_val = get_Status(); return (reg_val & Status_ANEG_ACK_MASK) >> Status_ANEG_ACK_SHIFT; } static inline u_int8_t mem_get_Status_ANEG_ACK(u_int16_t reg_val){ return (reg_val & Status_ANEG_ACK_MASK) >> Status_ANEG_ACK_SHIFT; } static inline void mem_set_Status_ANEG_ACK(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_ANEG_ACK_MASK) | ((bit_val << Status_ANEG_ACK_SHIFT) & Status_ANEG_ACK_MASK); } static inline u_int8_t get_Status_REM_FLT(void){ u_int16_t reg_val; reg_val = get_Status(); return (reg_val & Status_REM_FLT_MASK) >> Status_REM_FLT_SHIFT; } static inline u_int8_t mem_get_Status_REM_FLT(u_int16_t reg_val){ return (reg_val & Status_REM_FLT_MASK) >> Status_REM_FLT_SHIFT; } static inline void mem_set_Status_REM_FLT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_REM_FLT_MASK) | ((bit_val << Status_REM_FLT_SHIFT) & Status_REM_FLT_MASK); } static inline u_int8_t get_Status_CAP_ANEG(void){ u_int16_t reg_val; reg_val = get_Status(); return (reg_val & Status_CAP_ANEG_MASK) >> Status_CAP_ANEG_SHIFT; } static inline u_int8_t mem_get_Status_CAP_ANEG(u_int16_t reg_val){ return (reg_val & Status_CAP_ANEG_MASK) >> Status_CAP_ANEG_SHIFT; } static inline void mem_set_Status_CAP_ANEG(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_CAP_ANEG_MASK) | ((bit_val << Status_CAP_ANEG_SHIFT) & Status_CAP_ANEG_MASK); } static inline u_int8_t get_Status_LINK(void){ u_int16_t reg_val; reg_val = get_Status(); return (reg_val & Status_LINK_MASK) >> Status_LINK_SHIFT; } static inline u_int8_t mem_get_Status_LINK(u_int16_t reg_val){ return (reg_val & Status_LINK_MASK) >> Status_LINK_SHIFT; } static inline void mem_set_Status_LINK(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_LINK_MASK) | ((bit_val << Status_LINK_SHIFT) & Status_LINK_MASK); } static inline u_int8_t get_Status_JAB(void){ u_int16_t reg_val; reg_val = get_Status(); return (reg_val & Status_JAB_MASK) >> Status_JAB_SHIFT; } static inline u_int8_t mem_get_Status_JAB(u_int16_t reg_val){ return (reg_val & Status_JAB_MASK) >> Status_JAB_SHIFT; } static inline void mem_set_Status_JAB(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_JAB_MASK) | ((bit_val << Status_JAB_SHIFT) & Status_JAB_MASK); } static inline u_int8_t get_Status_EXREG(void){ u_int16_t reg_val; reg_val = get_Status(); return (reg_val & Status_EXREG_MASK) >> Status_EXREG_SHIFT; } static inline u_int8_t mem_get_Status_EXREG(u_int16_t reg_val){ return (reg_val & Status_EXREG_MASK) >> Status_EXREG_SHIFT; } static inline void mem_set_Status_EXREG(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_EXREG_MASK) | ((bit_val << Status_EXREG_SHIFT) & Status_EXREG_MASK); } /* accesing register PHY_ID1 (read only) */ static inline u_int16_t get_PHY_ID1(void){ u_int16_t val; val = _raw_read_PHY_ID1(); return val; } static inline u_int16_t get_PHY_ID1_VENDOR(void){ u_int16_t reg_val; reg_val = get_PHY_ID1(); return (reg_val & PHY_ID1_VENDOR_MASK) >> PHY_ID1_VENDOR_SHIFT; } static inline u_int16_t mem_get_PHY_ID1_VENDOR(u_int16_t reg_val){ return (reg_val & PHY_ID1_VENDOR_MASK) >> PHY_ID1_VENDOR_SHIFT; } static inline void mem_set_PHY_ID1_VENDOR(u_int16_t *reg_val, u_int16_t bit_val){ *reg_val = (*reg_val & ~PHY_ID1_VENDOR_MASK) | ((bit_val << PHY_ID1_VENDOR_SHIFT) & PHY_ID1_VENDOR_MASK); } /* accesing register PHY_ID2 (read only) */ static inline u_int16_t get_PHY_ID2(void){ u_int16_t val; val = _raw_read_PHY_ID2(); return val; } static inline u_int8_t get_PHY_ID2_OUILSB(void){ u_int16_t reg_val; reg_val = get_PHY_ID2(); return (reg_val & PHY_ID2_OUILSB_MASK) >> PHY_ID2_OUILSB_SHIFT; } static inline u_int8_t mem_get_PHY_ID2_OUILSB(u_int16_t reg_val){ return (reg_val & PHY_ID2_OUILSB_MASK) >> PHY_ID2_OUILSB_SHIFT; } static inline void mem_set_PHY_ID2_OUILSB(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~PHY_ID2_OUILSB_MASK) | ((bit_val << PHY_ID2_OUILSB_SHIFT) & PHY_ID2_OUILSB_MASK); } static inline u_int8_t get_PHY_ID2_MFGR(void){ u_int16_t reg_val; reg_val = get_PHY_ID2(); return (reg_val & PHY_ID2_MFGR_MASK) >> PHY_ID2_MFGR_SHIFT; } static inline u_int8_t mem_get_PHY_ID2_MFGR(u_int16_t reg_val){ return (reg_val & PHY_ID2_MFGR_MASK) >> PHY_ID2_MFGR_SHIFT; } static inline void mem_set_PHY_ID2_MFGR(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~PHY_ID2_MFGR_MASK) | ((bit_val << PHY_ID2_MFGR_SHIFT) & PHY_ID2_MFGR_MASK); } static inline u_int8_t get_PHY_ID2_REV(void){ u_int16_t reg_val; reg_val = get_PHY_ID2(); return (reg_val & PHY_ID2_REV_MASK) >> PHY_ID2_REV_SHIFT; } static inline u_int8_t mem_get_PHY_ID2_REV(u_int16_t reg_val){ return (reg_val & PHY_ID2_REV_MASK) >> PHY_ID2_REV_SHIFT; } static inline void mem_set_PHY_ID2_REV(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~PHY_ID2_REV_MASK) | ((bit_val << PHY_ID2_REV_SHIFT) & PHY_ID2_REV_MASK); } /* accesing register ANA (read write) */ static inline u_int16_t get_ANA(void){ u_int16_t val; val = _raw_read_ANA(); return val; } static inline void set_ANA(u_int16_t val){ _raw_write_ANA(val); } static inline u_int8_t get_ANA_NP(void){ u_int16_t reg_val; reg_val = get_ANA(); return (reg_val & ANA_NP_MASK) >> ANA_NP_SHIFT; } /*NP skipped since other bits are explicit */ static inline u_int8_t mem_get_ANA_NP(u_int16_t reg_val){ return (reg_val & ANA_NP_MASK) >> ANA_NP_SHIFT; } static inline void mem_set_ANA_NP(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ANA_NP_MASK) | ((bit_val << ANA_NP_SHIFT) & ANA_NP_MASK); } static inline u_int8_t get_ANA_ACK(void){ u_int16_t reg_val; reg_val = get_ANA(); return (reg_val & ANA_ACK_MASK) >> ANA_ACK_SHIFT; } static inline u_int8_t mem_get_ANA_ACK(u_int16_t reg_val){ return (reg_val & ANA_ACK_MASK) >> ANA_ACK_SHIFT; } static inline void mem_set_ANA_ACK(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ANA_ACK_MASK) | ((bit_val << ANA_ACK_SHIFT) & ANA_ACK_MASK); } static inline u_int8_t get_ANA_RF(void){ u_int16_t reg_val; reg_val = get_ANA(); return (reg_val & ANA_RF_MASK) >> ANA_RF_SHIFT; } /*RF skipped since other bits are explicit */ static inline u_int8_t mem_get_ANA_RF(u_int16_t reg_val){ return (reg_val & ANA_RF_MASK) >> ANA_RF_SHIFT; } static inline void mem_set_ANA_RF(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ANA_RF_MASK) | ((bit_val << ANA_RF_SHIFT) & ANA_RF_MASK); } static inline u_int8_t get_ANA_T4(void){ u_int16_t reg_val; reg_val = get_ANA(); return (reg_val & ANA_T4_MASK) >> ANA_T4_SHIFT; } /*T4 skipped since other bits are explicit */ static inline u_int8_t mem_get_ANA_T4(u_int16_t reg_val){ return (reg_val & ANA_T4_MASK) >> ANA_T4_SHIFT; } static inline void mem_set_ANA_T4(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ANA_T4_MASK) | ((bit_val << ANA_T4_SHIFT) & ANA_T4_MASK); } static inline u_int8_t get_ANA_TX_FDX(void){ u_int16_t reg_val; reg_val = get_ANA(); return (reg_val & ANA_TX_FDX_MASK) >> ANA_TX_FDX_SHIFT; } /*TX_FDX skipped since other bits are explicit */ static inline u_int8_t mem_get_ANA_TX_FDX(u_int16_t reg_val){ return (reg_val & ANA_TX_FDX_MASK) >> ANA_TX_FDX_SHIFT; } static inline void mem_set_ANA_TX_FDX(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ANA_TX_FDX_MASK) | ((bit_val << ANA_TX_FDX_SHIFT) & ANA_TX_FDX_MASK); } static inline u_int8_t get_ANA_TX_HDX(void){ u_int16_t reg_val; reg_val = get_ANA(); return (reg_val & ANA_TX_HDX_MASK) >> ANA_TX_HDX_SHIFT; } /*TX_HDX skipped since other bits are explicit */ static inline u_int8_t mem_get_ANA_TX_HDX(u_int16_t reg_val){ return (reg_val & ANA_TX_HDX_MASK) >> ANA_TX_HDX_SHIFT; } static inline void mem_set_ANA_TX_HDX(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ANA_TX_HDX_MASK) | ((bit_val << ANA_TX_HDX_SHIFT) & ANA_TX_HDX_MASK); } static inline u_int8_t get_ANA_TEN_FDX(void){ u_int16_t reg_val; reg_val = get_ANA(); return (reg_val & ANA_TEN_FDX_MASK) >> ANA_TEN_FDX_SHIFT; } /*TEN_FDX skipped since other bits are explicit */ static inline u_int8_t mem_get_ANA_TEN_FDX(u_int16_t reg_val){ return (reg_val & ANA_TEN_FDX_MASK) >> ANA_TEN_FDX_SHIFT; } static inline void mem_set_ANA_TEN_FDX(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ANA_TEN_FDX_MASK) | ((bit_val << ANA_TEN_FDX_SHIFT) & ANA_TEN_FDX_MASK); } static inline u_int8_t get_ANA_TEN_HDX(void){ u_int16_t reg_val; reg_val = get_ANA(); return (reg_val & ANA_TEN_HDX_MASK) >> ANA_TEN_HDX_SHIFT; } /*TEN_HDX skipped since other bits are explicit */ static inline u_int8_t mem_get_ANA_TEN_HDX(u_int16_t reg_val){ return (reg_val & ANA_TEN_HDX_MASK) >> ANA_TEN_HDX_SHIFT; } static inline void mem_set_ANA_TEN_HDX(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ANA_TEN_HDX_MASK) | ((bit_val << ANA_TEN_HDX_SHIFT) & ANA_TEN_HDX_MASK); } static inline u_int8_t get_ANA_CSMA(void){ u_int16_t reg_val; reg_val = get_ANA(); return (reg_val & ANA_CSMA_MASK) >> ANA_CSMA_SHIFT; } /*CSMA skipped since other bits are explicit */ static inline u_int8_t mem_get_ANA_CSMA(u_int16_t reg_val){ return (reg_val & ANA_CSMA_MASK) >> ANA_CSMA_SHIFT; } static inline void mem_set_ANA_CSMA(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ANA_CSMA_MASK) | ((bit_val << ANA_CSMA_SHIFT) & ANA_CSMA_MASK); } /* accesing register ANREC (read only) */ static inline u_int16_t get_ANREC(void){ u_int16_t val; val = _raw_read_ANREC(); return val; } static inline u_int8_t get_ANREC_NP(void){ u_int16_t reg_val; reg_val = get_ANREC(); return (reg_val & ANREC_NP_MASK) >> ANREC_NP_SHIFT; } static inline u_int8_t mem_get_ANREC_NP(u_int16_t reg_val){ return (reg_val & ANREC_NP_MASK) >> ANREC_NP_SHIFT; } static inline void mem_set_ANREC_NP(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ANREC_NP_MASK) | ((bit_val << ANREC_NP_SHIFT) & ANREC_NP_MASK); } static inline u_int8_t get_ANREC_ACK(void){ u_int16_t reg_val; reg_val = get_ANREC(); return (reg_val & ANREC_ACK_MASK) >> ANREC_ACK_SHIFT; } static inline u_int8_t mem_get_ANREC_ACK(u_int16_t reg_val){ return (reg_val & ANREC_ACK_MASK) >> ANREC_ACK_SHIFT; } static inline void mem_set_ANREC_ACK(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ANREC_ACK_MASK) | ((bit_val << ANREC_ACK_SHIFT) & ANREC_ACK_MASK); } static inline u_int8_t get_ANREC_RF(void){ u_int16_t reg_val; reg_val = get_ANREC(); return (reg_val & ANREC_RF_MASK) >> ANREC_RF_SHIFT; } static inline u_int8_t mem_get_ANREC_RF(u_int16_t reg_val){ return (reg_val & ANREC_RF_MASK) >> ANREC_RF_SHIFT; } static inline void mem_set_ANREC_RF(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ANREC_RF_MASK) | ((bit_val << ANREC_RF_SHIFT) & ANREC_RF_MASK); } static inline u_int8_t get_ANREC_T4(void){ u_int16_t reg_val; reg_val = get_ANREC(); return (reg_val & ANREC_T4_MASK) >> ANREC_T4_SHIFT; } static inline u_int8_t mem_get_ANREC_T4(u_int16_t reg_val){ return (reg_val & ANREC_T4_MASK) >> ANREC_T4_SHIFT; } static inline void mem_set_ANREC_T4(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ANREC_T4_MASK) | ((bit_val << ANREC_T4_SHIFT) & ANREC_T4_MASK); } static inline u_int8_t get_ANREC_TX_FDX(void){ u_int16_t reg_val; reg_val = get_ANREC(); return (reg_val & ANREC_TX_FDX_MASK) >> ANREC_TX_FDX_SHIFT; } static inline u_int8_t mem_get_ANREC_TX_FDX(u_int16_t reg_val){ return (reg_val & ANREC_TX_FDX_MASK) >> ANREC_TX_FDX_SHIFT; } static inline void mem_set_ANREC_TX_FDX(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ANREC_TX_FDX_MASK) | ((bit_val << ANREC_TX_FDX_SHIFT) & ANREC_TX_FDX_MASK); } static inline u_int8_t get_ANREC_TX_HDX(void){ u_int16_t reg_val; reg_val = get_ANREC(); return (reg_val & ANREC_TX_HDX_MASK) >> ANREC_TX_HDX_SHIFT; } static inline u_int8_t mem_get_ANREC_TX_HDX(u_int16_t reg_val){ return (reg_val & ANREC_TX_HDX_MASK) >> ANREC_TX_HDX_SHIFT; } static inline void mem_set_ANREC_TX_HDX(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ANREC_TX_HDX_MASK) | ((bit_val << ANREC_TX_HDX_SHIFT) & ANREC_TX_HDX_MASK); } static inline u_int8_t get_ANREC_TEN_FDX(void){ u_int16_t reg_val; reg_val = get_ANREC(); return (reg_val & ANREC_TEN_FDX_MASK) >> ANREC_TEN_FDX_SHIFT; } static inline u_int8_t mem_get_ANREC_TEN_FDX(u_int16_t reg_val){ return (reg_val & ANREC_TEN_FDX_MASK) >> ANREC_TEN_FDX_SHIFT; } static inline void mem_set_ANREC_TEN_FDX(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ANREC_TEN_FDX_MASK) | ((bit_val << ANREC_TEN_FDX_SHIFT) & ANREC_TEN_FDX_MASK); } static inline u_int8_t get_ANREC_TEN_HDX(void){ u_int16_t reg_val; reg_val = get_ANREC(); return (reg_val & ANREC_TEN_HDX_MASK) >> ANREC_TEN_HDX_SHIFT; } static inline u_int8_t mem_get_ANREC_TEN_HDX(u_int16_t reg_val){ return (reg_val & ANREC_TEN_HDX_MASK) >> ANREC_TEN_HDX_SHIFT; } static inline void mem_set_ANREC_TEN_HDX(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ANREC_TEN_HDX_MASK) | ((bit_val << ANREC_TEN_HDX_SHIFT) & ANREC_TEN_HDX_MASK); } static inline u_int8_t get_ANREC_CSMA(void){ u_int16_t reg_val; reg_val = get_ANREC(); return (reg_val & ANREC_CSMA_MASK) >> ANREC_CSMA_SHIFT; } static inline u_int8_t mem_get_ANREC_CSMA(u_int16_t reg_val){ return (reg_val & ANREC_CSMA_MASK) >> ANREC_CSMA_SHIFT; } static inline void mem_set_ANREC_CSMA(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~ANREC_CSMA_MASK) | ((bit_val << ANREC_CSMA_SHIFT) & ANREC_CSMA_MASK); } /* accesing register Config1 (read write) */ static inline u_int16_t get_Config1(void){ u_int16_t val; val = _raw_read_Config1(); return val; } static inline void set_Config1(u_int16_t val){ _raw_write_Config1(val); } static inline u_int8_t get_Config1_LNKDIS(void){ u_int16_t reg_val; reg_val = get_Config1(); return (reg_val & Config1_LNKDIS_MASK) >> Config1_LNKDIS_SHIFT; } static inline void set_Config1_LNKDIS(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Config1(); reg_val = (reg_val & ~Config1_RSV_11_12_MASK) | ((0 << Config1_RSV_11_12_SHIFT) & Config1_RSV_11_12_MASK); reg_val = (reg_val & ~Config1_LNKDIS_MASK) | ((bit_val << Config1_LNKDIS_SHIFT) & Config1_LNKDIS_MASK); set_Config1(reg_val); } static inline u_int8_t mem_get_Config1_LNKDIS(u_int16_t reg_val){ return (reg_val & Config1_LNKDIS_MASK) >> Config1_LNKDIS_SHIFT; } static inline void mem_set_Config1_LNKDIS(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Config1_LNKDIS_MASK) | ((bit_val << Config1_LNKDIS_SHIFT) & Config1_LNKDIS_MASK); } static inline u_int8_t get_Config1_XMTDIS(void){ u_int16_t reg_val; reg_val = get_Config1(); return (reg_val & Config1_XMTDIS_MASK) >> Config1_XMTDIS_SHIFT; } static inline void set_Config1_XMTDIS(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Config1(); reg_val = (reg_val & ~Config1_RSV_11_12_MASK) | ((0 << Config1_RSV_11_12_SHIFT) & Config1_RSV_11_12_MASK); reg_val = (reg_val & ~Config1_XMTDIS_MASK) | ((bit_val << Config1_XMTDIS_SHIFT) & Config1_XMTDIS_MASK); set_Config1(reg_val); } static inline u_int8_t mem_get_Config1_XMTDIS(u_int16_t reg_val){ return (reg_val & Config1_XMTDIS_MASK) >> Config1_XMTDIS_SHIFT; } static inline void mem_set_Config1_XMTDIS(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Config1_XMTDIS_MASK) | ((bit_val << Config1_XMTDIS_SHIFT) & Config1_XMTDIS_MASK); } static inline u_int8_t get_Config1_XMTPDN(void){ u_int16_t reg_val; reg_val = get_Config1(); return (reg_val & Config1_XMTPDN_MASK) >> Config1_XMTPDN_SHIFT; } static inline void set_Config1_XMTPDN(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Config1(); reg_val = (reg_val & ~Config1_RSV_11_12_MASK) | ((0 << Config1_RSV_11_12_SHIFT) & Config1_RSV_11_12_MASK); reg_val = (reg_val & ~Config1_XMTPDN_MASK) | ((bit_val << Config1_XMTPDN_SHIFT) & Config1_XMTPDN_MASK); set_Config1(reg_val); } static inline u_int8_t mem_get_Config1_XMTPDN(u_int16_t reg_val){ return (reg_val & Config1_XMTPDN_MASK) >> Config1_XMTPDN_SHIFT; } static inline void mem_set_Config1_XMTPDN(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Config1_XMTPDN_MASK) | ((bit_val << Config1_XMTPDN_SHIFT) & Config1_XMTPDN_MASK); } static inline u_int8_t get_Config1_BYPSCR(void){ u_int16_t reg_val; reg_val = get_Config1(); return (reg_val & Config1_BYPSCR_MASK) >> Config1_BYPSCR_SHIFT; } static inline void set_Config1_BYPSCR(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Config1(); reg_val = (reg_val & ~Config1_RSV_11_12_MASK) | ((0 << Config1_RSV_11_12_SHIFT) & Config1_RSV_11_12_MASK); reg_val = (reg_val & ~Config1_BYPSCR_MASK) | ((bit_val << Config1_BYPSCR_SHIFT) & Config1_BYPSCR_MASK); set_Config1(reg_val); } static inline u_int8_t mem_get_Config1_BYPSCR(u_int16_t reg_val){ return (reg_val & Config1_BYPSCR_MASK) >> Config1_BYPSCR_SHIFT; } static inline void mem_set_Config1_BYPSCR(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Config1_BYPSCR_MASK) | ((bit_val << Config1_BYPSCR_SHIFT) & Config1_BYPSCR_MASK); } static inline u_int8_t get_Config1_UNSCDS(void){ u_int16_t reg_val; reg_val = get_Config1(); return (reg_val & Config1_UNSCDS_MASK) >> Config1_UNSCDS_SHIFT; } static inline void set_Config1_UNSCDS(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Config1(); reg_val = (reg_val & ~Config1_RSV_11_12_MASK) | ((0 << Config1_RSV_11_12_SHIFT) & Config1_RSV_11_12_MASK); reg_val = (reg_val & ~Config1_UNSCDS_MASK) | ((bit_val << Config1_UNSCDS_SHIFT) & Config1_UNSCDS_MASK); set_Config1(reg_val); } static inline u_int8_t mem_get_Config1_UNSCDS(u_int16_t reg_val){ return (reg_val & Config1_UNSCDS_MASK) >> Config1_UNSCDS_SHIFT; } static inline void mem_set_Config1_UNSCDS(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Config1_UNSCDS_MASK) | ((bit_val << Config1_UNSCDS_SHIFT) & Config1_UNSCDS_MASK); } static inline u_int8_t get_Config1_EQLZR(void){ u_int16_t reg_val; reg_val = get_Config1(); return (reg_val & Config1_EQLZR_MASK) >> Config1_EQLZR_SHIFT; } static inline void set_Config1_EQLZR(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Config1(); reg_val = (reg_val & ~Config1_RSV_11_12_MASK) | ((0 << Config1_RSV_11_12_SHIFT) & Config1_RSV_11_12_MASK); reg_val = (reg_val & ~Config1_EQLZR_MASK) | ((bit_val << Config1_EQLZR_SHIFT) & Config1_EQLZR_MASK); set_Config1(reg_val); } static inline u_int8_t mem_get_Config1_EQLZR(u_int16_t reg_val){ return (reg_val & Config1_EQLZR_MASK) >> Config1_EQLZR_SHIFT; } static inline void mem_set_Config1_EQLZR(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Config1_EQLZR_MASK) | ((bit_val << Config1_EQLZR_SHIFT) & Config1_EQLZR_MASK); } static inline u_int8_t get_Config1_CABLE(void){ u_int16_t reg_val; reg_val = get_Config1(); return (reg_val & Config1_CABLE_MASK) >> Config1_CABLE_SHIFT; } static inline void set_Config1_CABLE(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Config1(); reg_val = (reg_val & ~Config1_RSV_11_12_MASK) | ((0 << Config1_RSV_11_12_SHIFT) & Config1_RSV_11_12_MASK); reg_val = (reg_val & ~Config1_CABLE_MASK) | ((bit_val << Config1_CABLE_SHIFT) & Config1_CABLE_MASK); set_Config1(reg_val); } static inline u_int8_t mem_get_Config1_CABLE(u_int16_t reg_val){ return (reg_val & Config1_CABLE_MASK) >> Config1_CABLE_SHIFT; } static inline void mem_set_Config1_CABLE(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Config1_CABLE_MASK) | ((bit_val << Config1_CABLE_SHIFT) & Config1_CABLE_MASK); } static inline u_int8_t get_Config1_RLVL(void){ u_int16_t reg_val; reg_val = get_Config1(); return (reg_val & Config1_RLVL_MASK) >> Config1_RLVL_SHIFT; } static inline void set_Config1_RLVL(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Config1(); reg_val = (reg_val & ~Config1_RSV_11_12_MASK) | ((0 << Config1_RSV_11_12_SHIFT) & Config1_RSV_11_12_MASK); reg_val = (reg_val & ~Config1_RLVL_MASK) | ((bit_val << Config1_RLVL_SHIFT) & Config1_RLVL_MASK); set_Config1(reg_val); } static inline u_int8_t mem_get_Config1_RLVL(u_int16_t reg_val){ return (reg_val & Config1_RLVL_MASK) >> Config1_RLVL_SHIFT; } static inline void mem_set_Config1_RLVL(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Config1_RLVL_MASK) | ((bit_val << Config1_RLVL_SHIFT) & Config1_RLVL_MASK); } static inline u_int8_t get_Config1_TLVL(void){ u_int16_t reg_val; reg_val = get_Config1(); return (reg_val & Config1_TLVL_MASK) >> Config1_TLVL_SHIFT; } static inline void set_Config1_TLVL(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Config1(); reg_val = (reg_val & ~Config1_RSV_11_12_MASK) | ((0 << Config1_RSV_11_12_SHIFT) & Config1_RSV_11_12_MASK); reg_val = (reg_val & ~Config1_TLVL_MASK) | ((bit_val << Config1_TLVL_SHIFT) & Config1_TLVL_MASK); set_Config1(reg_val); } static inline u_int8_t mem_get_Config1_TLVL(u_int16_t reg_val){ return (reg_val & Config1_TLVL_MASK) >> Config1_TLVL_SHIFT; } static inline void mem_set_Config1_TLVL(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Config1_TLVL_MASK) | ((bit_val << Config1_TLVL_SHIFT) & Config1_TLVL_MASK); } static inline u_int8_t get_Config1_TRF(void){ u_int16_t reg_val; reg_val = get_Config1(); return (reg_val & Config1_TRF_MASK) >> Config1_TRF_SHIFT; } static inline void set_Config1_TRF(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Config1(); reg_val = (reg_val & ~Config1_RSV_11_12_MASK) | ((0 << Config1_RSV_11_12_SHIFT) & Config1_RSV_11_12_MASK); reg_val = (reg_val & ~Config1_TRF_MASK) | ((bit_val << Config1_TRF_SHIFT) & Config1_TRF_MASK); set_Config1(reg_val); } static inline u_int8_t mem_get_Config1_TRF(u_int16_t reg_val){ return (reg_val & Config1_TRF_MASK) >> Config1_TRF_SHIFT; } static inline void mem_set_Config1_TRF(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Config1_TRF_MASK) | ((bit_val << Config1_TRF_SHIFT) & Config1_TRF_MASK); } /* accesing register Config2 (read write) */ static inline u_int16_t get_Config2(void){ u_int16_t val; val = _raw_read_Config2(); return val; } static inline void set_Config2(u_int16_t val){ _raw_write_Config2(val); } static inline u_int8_t get_Config2_APOLDIS(void){ u_int16_t reg_val; reg_val = get_Config2(); return (reg_val & Config2_APOLDIS_MASK) >> Config2_APOLDIS_SHIFT; } static inline void set_Config2_APOLDIS(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Config2(); reg_val = (reg_val & ~Config2_APOLDIS_MASK) | ((bit_val << Config2_APOLDIS_SHIFT) & Config2_APOLDIS_MASK); set_Config2(reg_val); } static inline u_int8_t mem_get_Config2_APOLDIS(u_int16_t reg_val){ return (reg_val & Config2_APOLDIS_MASK) >> Config2_APOLDIS_SHIFT; } static inline void mem_set_Config2_APOLDIS(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Config2_APOLDIS_MASK) | ((bit_val << Config2_APOLDIS_SHIFT) & Config2_APOLDIS_MASK); } static inline u_int8_t get_Config2_JABDIS(void){ u_int16_t reg_val; reg_val = get_Config2(); return (reg_val & Config2_JABDIS_MASK) >> Config2_JABDIS_SHIFT; } static inline void set_Config2_JABDIS(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Config2(); reg_val = (reg_val & ~Config2_JABDIS_MASK) | ((bit_val << Config2_JABDIS_SHIFT) & Config2_JABDIS_MASK); set_Config2(reg_val); } static inline u_int8_t mem_get_Config2_JABDIS(u_int16_t reg_val){ return (reg_val & Config2_JABDIS_MASK) >> Config2_JABDIS_SHIFT; } static inline void mem_set_Config2_JABDIS(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Config2_JABDIS_MASK) | ((bit_val << Config2_JABDIS_SHIFT) & Config2_JABDIS_MASK); } static inline u_int8_t get_Config2_MREG(void){ u_int16_t reg_val; reg_val = get_Config2(); return (reg_val & Config2_MREG_MASK) >> Config2_MREG_SHIFT; } static inline void set_Config2_MREG(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Config2(); reg_val = (reg_val & ~Config2_MREG_MASK) | ((bit_val << Config2_MREG_SHIFT) & Config2_MREG_MASK); set_Config2(reg_val); } static inline u_int8_t mem_get_Config2_MREG(u_int16_t reg_val){ return (reg_val & Config2_MREG_MASK) >> Config2_MREG_SHIFT; } static inline void mem_set_Config2_MREG(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Config2_MREG_MASK) | ((bit_val << Config2_MREG_SHIFT) & Config2_MREG_MASK); } static inline u_int8_t get_Config2_INTMDIO(void){ u_int16_t reg_val; reg_val = get_Config2(); return (reg_val & Config2_INTMDIO_MASK) >> Config2_INTMDIO_SHIFT; } static inline void set_Config2_INTMDIO(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Config2(); reg_val = (reg_val & ~Config2_INTMDIO_MASK) | ((bit_val << Config2_INTMDIO_SHIFT) & Config2_INTMDIO_MASK); set_Config2(reg_val); } static inline u_int8_t mem_get_Config2_INTMDIO(u_int16_t reg_val){ return (reg_val & Config2_INTMDIO_MASK) >> Config2_INTMDIO_SHIFT; } static inline void mem_set_Config2_INTMDIO(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Config2_INTMDIO_MASK) | ((bit_val << Config2_INTMDIO_SHIFT) & Config2_INTMDIO_MASK); } /* accesing register Status_Output (read only) */ static inline u_int16_t get_Status_Output(void){ u_int16_t val; val = _raw_read_Status_Output(); return val; } static inline u_int8_t get_Status_Output_INT(void){ u_int16_t reg_val; reg_val = get_Status_Output(); return (reg_val & Status_Output_INT_MASK) >> Status_Output_INT_SHIFT; } static inline u_int8_t mem_get_Status_Output_INT(u_int16_t reg_val){ return (reg_val & Status_Output_INT_MASK) >> Status_Output_INT_SHIFT; } static inline void mem_set_Status_Output_INT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_Output_INT_MASK) | ((bit_val << Status_Output_INT_SHIFT) & Status_Output_INT_MASK); } static inline u_int8_t get_Status_Output_LNKFAIL(void){ u_int16_t reg_val; reg_val = get_Status_Output(); return (reg_val & Status_Output_LNKFAIL_MASK) >> Status_Output_LNKFAIL_SHIFT; } static inline u_int8_t mem_get_Status_Output_LNKFAIL(u_int16_t reg_val){ return (reg_val & Status_Output_LNKFAIL_MASK) >> Status_Output_LNKFAIL_SHIFT; } static inline void mem_set_Status_Output_LNKFAIL(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_Output_LNKFAIL_MASK) | ((bit_val << Status_Output_LNKFAIL_SHIFT) & Status_Output_LNKFAIL_MASK); } static inline u_int8_t get_Status_Output_LOSSSYNC(void){ u_int16_t reg_val; reg_val = get_Status_Output(); return (reg_val & Status_Output_LOSSSYNC_MASK) >> Status_Output_LOSSSYNC_SHIFT; } static inline u_int8_t mem_get_Status_Output_LOSSSYNC(u_int16_t reg_val){ return (reg_val & Status_Output_LOSSSYNC_MASK) >> Status_Output_LOSSSYNC_SHIFT; } static inline void mem_set_Status_Output_LOSSSYNC(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_Output_LOSSSYNC_MASK) | ((bit_val << Status_Output_LOSSSYNC_SHIFT) & Status_Output_LOSSSYNC_MASK); } static inline u_int8_t get_Status_Output_CWRD(void){ u_int16_t reg_val; reg_val = get_Status_Output(); return (reg_val & Status_Output_CWRD_MASK) >> Status_Output_CWRD_SHIFT; } static inline u_int8_t mem_get_Status_Output_CWRD(u_int16_t reg_val){ return (reg_val & Status_Output_CWRD_MASK) >> Status_Output_CWRD_SHIFT; } static inline void mem_set_Status_Output_CWRD(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_Output_CWRD_MASK) | ((bit_val << Status_Output_CWRD_SHIFT) & Status_Output_CWRD_MASK); } static inline u_int8_t get_Status_Output_SSD(void){ u_int16_t reg_val; reg_val = get_Status_Output(); return (reg_val & Status_Output_SSD_MASK) >> Status_Output_SSD_SHIFT; } static inline u_int8_t mem_get_Status_Output_SSD(u_int16_t reg_val){ return (reg_val & Status_Output_SSD_MASK) >> Status_Output_SSD_SHIFT; } static inline void mem_set_Status_Output_SSD(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_Output_SSD_MASK) | ((bit_val << Status_Output_SSD_SHIFT) & Status_Output_SSD_MASK); } static inline u_int8_t get_Status_Output_ESD(void){ u_int16_t reg_val; reg_val = get_Status_Output(); return (reg_val & Status_Output_ESD_MASK) >> Status_Output_ESD_SHIFT; } static inline u_int8_t mem_get_Status_Output_ESD(u_int16_t reg_val){ return (reg_val & Status_Output_ESD_MASK) >> Status_Output_ESD_SHIFT; } static inline void mem_set_Status_Output_ESD(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_Output_ESD_MASK) | ((bit_val << Status_Output_ESD_SHIFT) & Status_Output_ESD_MASK); } static inline u_int8_t get_Status_Output_RPOL(void){ u_int16_t reg_val; reg_val = get_Status_Output(); return (reg_val & Status_Output_RPOL_MASK) >> Status_Output_RPOL_SHIFT; } static inline u_int8_t mem_get_Status_Output_RPOL(u_int16_t reg_val){ return (reg_val & Status_Output_RPOL_MASK) >> Status_Output_RPOL_SHIFT; } static inline void mem_set_Status_Output_RPOL(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_Output_RPOL_MASK) | ((bit_val << Status_Output_RPOL_SHIFT) & Status_Output_RPOL_MASK); } static inline u_int8_t get_Status_Output_JAB(void){ u_int16_t reg_val; reg_val = get_Status_Output(); return (reg_val & Status_Output_JAB_MASK) >> Status_Output_JAB_SHIFT; } static inline u_int8_t mem_get_Status_Output_JAB(u_int16_t reg_val){ return (reg_val & Status_Output_JAB_MASK) >> Status_Output_JAB_SHIFT; } static inline void mem_set_Status_Output_JAB(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_Output_JAB_MASK) | ((bit_val << Status_Output_JAB_SHIFT) & Status_Output_JAB_MASK); } static inline u_int8_t get_Status_Output_SPDDET(void){ u_int16_t reg_val; reg_val = get_Status_Output(); return (reg_val & Status_Output_SPDDET_MASK) >> Status_Output_SPDDET_SHIFT; } static inline u_int8_t mem_get_Status_Output_SPDDET(u_int16_t reg_val){ return (reg_val & Status_Output_SPDDET_MASK) >> Status_Output_SPDDET_SHIFT; } static inline void mem_set_Status_Output_SPDDET(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_Output_SPDDET_MASK) | ((bit_val << Status_Output_SPDDET_SHIFT) & Status_Output_SPDDET_MASK); } static inline u_int8_t get_Status_Output_DPLXDET(void){ u_int16_t reg_val; reg_val = get_Status_Output(); return (reg_val & Status_Output_DPLXDET_MASK) >> Status_Output_DPLXDET_SHIFT; } static inline u_int8_t mem_get_Status_Output_DPLXDET(u_int16_t reg_val){ return (reg_val & Status_Output_DPLXDET_MASK) >> Status_Output_DPLXDET_SHIFT; } static inline void mem_set_Status_Output_DPLXDET(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Status_Output_DPLXDET_MASK) | ((bit_val << Status_Output_DPLXDET_SHIFT) & Status_Output_DPLXDET_MASK); } /* accesing register Mask (read write) */ static inline u_int16_t get_Mask(void){ u_int16_t val; val = _raw_read_Mask(); return val; } static inline void set_Mask(u_int16_t val){ _raw_write_Mask(val); } static inline u_int8_t get_Mask_MINT(void){ u_int16_t reg_val; reg_val = get_Mask(); return (reg_val & Mask_MINT_MASK) >> Mask_MINT_SHIFT; } static inline void set_Mask_MINT(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Mask(); reg_val = (reg_val & ~Mask_MINT_MASK) | ((bit_val << Mask_MINT_SHIFT) & Mask_MINT_MASK); set_Mask(reg_val); } static inline u_int8_t mem_get_Mask_MINT(u_int16_t reg_val){ return (reg_val & Mask_MINT_MASK) >> Mask_MINT_SHIFT; } static inline void mem_set_Mask_MINT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Mask_MINT_MASK) | ((bit_val << Mask_MINT_SHIFT) & Mask_MINT_MASK); } static inline u_int8_t get_Mask_MLNKFAIL(void){ u_int16_t reg_val; reg_val = get_Mask(); return (reg_val & Mask_MLNKFAIL_MASK) >> Mask_MLNKFAIL_SHIFT; } static inline void set_Mask_MLNKFAIL(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Mask(); reg_val = (reg_val & ~Mask_MLNKFAIL_MASK) | ((bit_val << Mask_MLNKFAIL_SHIFT) & Mask_MLNKFAIL_MASK); set_Mask(reg_val); } static inline u_int8_t mem_get_Mask_MLNKFAIL(u_int16_t reg_val){ return (reg_val & Mask_MLNKFAIL_MASK) >> Mask_MLNKFAIL_SHIFT; } static inline void mem_set_Mask_MLNKFAIL(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Mask_MLNKFAIL_MASK) | ((bit_val << Mask_MLNKFAIL_SHIFT) & Mask_MLNKFAIL_MASK); } static inline u_int8_t get_Mask_MLOSSSYN(void){ u_int16_t reg_val; reg_val = get_Mask(); return (reg_val & Mask_MLOSSSYN_MASK) >> Mask_MLOSSSYN_SHIFT; } static inline void set_Mask_MLOSSSYN(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Mask(); reg_val = (reg_val & ~Mask_MLOSSSYN_MASK) | ((bit_val << Mask_MLOSSSYN_SHIFT) & Mask_MLOSSSYN_MASK); set_Mask(reg_val); } static inline u_int8_t mem_get_Mask_MLOSSSYN(u_int16_t reg_val){ return (reg_val & Mask_MLOSSSYN_MASK) >> Mask_MLOSSSYN_SHIFT; } static inline void mem_set_Mask_MLOSSSYN(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Mask_MLOSSSYN_MASK) | ((bit_val << Mask_MLOSSSYN_SHIFT) & Mask_MLOSSSYN_MASK); } static inline u_int8_t get_Mask_MCWRD(void){ u_int16_t reg_val; reg_val = get_Mask(); return (reg_val & Mask_MCWRD_MASK) >> Mask_MCWRD_SHIFT; } static inline void set_Mask_MCWRD(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Mask(); reg_val = (reg_val & ~Mask_MCWRD_MASK) | ((bit_val << Mask_MCWRD_SHIFT) & Mask_MCWRD_MASK); set_Mask(reg_val); } static inline u_int8_t mem_get_Mask_MCWRD(u_int16_t reg_val){ return (reg_val & Mask_MCWRD_MASK) >> Mask_MCWRD_SHIFT; } static inline void mem_set_Mask_MCWRD(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Mask_MCWRD_MASK) | ((bit_val << Mask_MCWRD_SHIFT) & Mask_MCWRD_MASK); } static inline u_int8_t get_Mask_MSSD(void){ u_int16_t reg_val; reg_val = get_Mask(); return (reg_val & Mask_MSSD_MASK) >> Mask_MSSD_SHIFT; } static inline void set_Mask_MSSD(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Mask(); reg_val = (reg_val & ~Mask_MSSD_MASK) | ((bit_val << Mask_MSSD_SHIFT) & Mask_MSSD_MASK); set_Mask(reg_val); } static inline u_int8_t mem_get_Mask_MSSD(u_int16_t reg_val){ return (reg_val & Mask_MSSD_MASK) >> Mask_MSSD_SHIFT; } static inline void mem_set_Mask_MSSD(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Mask_MSSD_MASK) | ((bit_val << Mask_MSSD_SHIFT) & Mask_MSSD_MASK); } static inline u_int8_t get_Mask_MESD(void){ u_int16_t reg_val; reg_val = get_Mask(); return (reg_val & Mask_MESD_MASK) >> Mask_MESD_SHIFT; } static inline void set_Mask_MESD(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Mask(); reg_val = (reg_val & ~Mask_MESD_MASK) | ((bit_val << Mask_MESD_SHIFT) & Mask_MESD_MASK); set_Mask(reg_val); } static inline u_int8_t mem_get_Mask_MESD(u_int16_t reg_val){ return (reg_val & Mask_MESD_MASK) >> Mask_MESD_SHIFT; } static inline void mem_set_Mask_MESD(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Mask_MESD_MASK) | ((bit_val << Mask_MESD_SHIFT) & Mask_MESD_MASK); } static inline u_int8_t get_Mask_MRPOL(void){ u_int16_t reg_val; reg_val = get_Mask(); return (reg_val & Mask_MRPOL_MASK) >> Mask_MRPOL_SHIFT; } static inline void set_Mask_MRPOL(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Mask(); reg_val = (reg_val & ~Mask_MRPOL_MASK) | ((bit_val << Mask_MRPOL_SHIFT) & Mask_MRPOL_MASK); set_Mask(reg_val); } static inline u_int8_t mem_get_Mask_MRPOL(u_int16_t reg_val){ return (reg_val & Mask_MRPOL_MASK) >> Mask_MRPOL_SHIFT; } static inline void mem_set_Mask_MRPOL(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Mask_MRPOL_MASK) | ((bit_val << Mask_MRPOL_SHIFT) & Mask_MRPOL_MASK); } static inline u_int8_t get_Mask_MJAB(void){ u_int16_t reg_val; reg_val = get_Mask(); return (reg_val & Mask_MJAB_MASK) >> Mask_MJAB_SHIFT; } static inline void set_Mask_MJAB(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Mask(); reg_val = (reg_val & ~Mask_MJAB_MASK) | ((bit_val << Mask_MJAB_SHIFT) & Mask_MJAB_MASK); set_Mask(reg_val); } static inline u_int8_t mem_get_Mask_MJAB(u_int16_t reg_val){ return (reg_val & Mask_MJAB_MASK) >> Mask_MJAB_SHIFT; } static inline void mem_set_Mask_MJAB(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Mask_MJAB_MASK) | ((bit_val << Mask_MJAB_SHIFT) & Mask_MJAB_MASK); } static inline u_int8_t get_Mask_MSPDDT(void){ u_int16_t reg_val; reg_val = get_Mask(); return (reg_val & Mask_MSPDDT_MASK) >> Mask_MSPDDT_SHIFT; } static inline void set_Mask_MSPDDT(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Mask(); reg_val = (reg_val & ~Mask_MSPDDT_MASK) | ((bit_val << Mask_MSPDDT_SHIFT) & Mask_MSPDDT_MASK); set_Mask(reg_val); } static inline u_int8_t mem_get_Mask_MSPDDT(u_int16_t reg_val){ return (reg_val & Mask_MSPDDT_MASK) >> Mask_MSPDDT_SHIFT; } static inline void mem_set_Mask_MSPDDT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Mask_MSPDDT_MASK) | ((bit_val << Mask_MSPDDT_SHIFT) & Mask_MSPDDT_MASK); } static inline u_int8_t get_Mask_MDPLDT(void){ u_int16_t reg_val; reg_val = get_Mask(); return (reg_val & Mask_MDPLDT_MASK) >> Mask_MDPLDT_SHIFT; } static inline void set_Mask_MDPLDT(u_int8_t bit_val){ u_int16_t reg_val = 0; reg_val = get_Mask(); reg_val = (reg_val & ~Mask_MDPLDT_MASK) | ((bit_val << Mask_MDPLDT_SHIFT) & Mask_MDPLDT_MASK); set_Mask(reg_val); } static inline u_int8_t mem_get_Mask_MDPLDT(u_int16_t reg_val){ return (reg_val & Mask_MDPLDT_MASK) >> Mask_MDPLDT_SHIFT; } static inline void mem_set_Mask_MDPLDT(u_int16_t *reg_val, u_int8_t bit_val){ *reg_val = (*reg_val & ~Mask_MDPLDT_MASK) | ((bit_val << Mask_MDPLDT_SHIFT) & Mask_MDPLDT_MASK); } /* accesing register Reserved (read write) */ static inline u_int16_t get_Reserved(void){ u_int16_t val; val = _raw_read_Reserved(); return val; } static inline void set_Reserved(u_int16_t val){ _raw_write_Reserved(val); }